ASIC Design Verification Engineer
About The Position
The MSIP UMC team is looking for an ASIC Design Verification Engineer to join their growing team. This team develops leading-edge DDR technologies powering data center and machine learning workloads and is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. The role involves all aspects of IP verification, including creating a verification architecture, defining test plans, developing verification environments, and verification closure/sign-off. The engineer will also participate in key technical leadership activities and collaborate with DV Architects and DV leads in shaping cutting-edge verification environments for current and future programs. As a key contributor, the role aims to drive and improve AMD’s abilities to deliver high-quality, industry-leading technologies to market. The NBIO Team fosters continuous technical innovation and career development.
Requirements
- BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.
- ASIC verification experience
- Strong understanding of digital design and computer architecture
- Strong understanding and experience in block-level constrained random verification
- Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments
- ASIC design knowledge and be able to debug System Verilog RTL code using simulation tools
Nice To Haves
- Experience in formal verification would be an asset
Responsibilities
- Collaborate with IP architects to come up with verification architecture, verification methodology, improvements, and development plans
- Taking on some key technical leadership responsibilities to help current DV leads and DV Architects
- Participate in verification of complex IP blocks and take end-to-end ownership of key features for all projects
- Work on test plans, verification environment development, regression, and coverage closure
- Develop modifying and maintaining VIP, libraries, verification environments, testcases (random and directed) using System Verilog/UVM/SystemC
- Triaging and Debugging Regressions
- Analyzing code and functional coverage
- Deploying industry-leading verification methodologies such as UVM and formal Verification
- Reproducing functional bugs found in post-silicon in dynamic simulation and/or formal verification environments
- Conducting and participating in code reviews
- Develop and maintain scripts and tools to continuously improve in engineering infrastructure, methodology and execution
Benefits
- AMD benefits at a glance
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
