ASIC Design Verification Engineer

Broadcom•Broomfield, CA

About The Position

This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency. We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers. This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Requirements

Self motivated personality with a strong presence to do things right.
Strong sense of teamwork and ability to work well with others.
Experience driving completion via coverage closure.
Skills with SV and UVM, well versed in OOP.
System Verilog (TB structures - Class, SVA, etc.)
UVM
VCS
Incisive
Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience

Nice To Haves

Scripting skills a + (Python, Perl, ...)

Responsibilities

Constrained random verification methodologies with experience driving completion via coverage closure.
Work with worldwide design and architecture teams to develop leading edge products.
All aspects of Design Verification will be involved, along with opportunities for technical leadership.