ASIC Design Engineering Technical Lead (Hybrid)

Cisco•San Jose, CA

2d•Hybrid

About The Position

Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of Front-End design including the development of programmable, scalable silicon architectures that power next-generation networking products.. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry! YOUR IMPACT Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Help define the process, methods, and tools for design and implementation of complex developments. Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure. Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation. Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon. Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges. Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team. Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation. Creates re-usable code that promotes efficiencies in new ways Influence system architecture and key design decisions across complex ASIC subsystems.

Requirements

Bachelor's degree in Electrical Engineering with 8+ years of ASIC design experience, or Master's degree in Electrical Engineering with 6+ years of ASIC design experience, or PhD in Electrical Engineering and 3+ years of ASIC design experience.
ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes.
Strong expertise in high-performance RTL design using Verilog/SystemVerilog.
Deep understanding of timing closure, power optimization, and clock gating techniques.
Experience with ASIC development flows including simulation, synthesis, and static timing analysis.

Nice To Haves

10+ years of ASIC design experience, delivering silicon from architecture and specification through tape-out.
Strong documentation, problem-solving, debug and technical communication skills
Experience working cross-functionally and collaborating with various technical teams
Problem solver who loves to tackle new challenges and a self-starter who is highly motivated and thrives on innovative technology.
Strong communicator in a team setting, enjoys working in a dynamic team environment, and is an out-of-the-box thinker.

Responsibilities

Define, design and take end to end Front-End ownership of ASIC subsystems to be deployed in a range of Cisco platforms.
Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products.
Help define the process, methods, and tools for design and implementation of complex developments.
Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure.
Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets.
Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon.
Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges.
Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team.
Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.
Creates re-usable code that promotes efficiencies in new ways
Influence system architecture and key design decisions across complex ASIC subsystems.

Benefits

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.
Please see the Cisco careers site to discover more benefits and perks.
Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.