ASIC Design Engineer

BLUE ORIGIN • Central, TX

1d

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. The ASIC Design Engineer contributes to the design of digital IP blocks for advanced Satellite communication ASICs. This role is an excellent opportunity to grow technical depth in RTL design, digital subsystem fundamentals, and cross-functional collaboration while helping deliver high-performance silicon for space and ground communication platforms.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related field.
• 0–2 years of ASIC digital design experience (internships, co-ops, academic projects, or research experience considered).
• Exposure to ASIC or FPGA development through coursework, projects, or internships.
• Foundational knowledge of SystemVerilog/Verilog RTL design and debug.
• Familiarity with digital design fundamentals, including synthesis and timing concepts.
• Awareness of PPA (power, performance, area) tradeoffs in digital design.
• Strong communication skills and the ability to collaborate across multidisciplinary teams.

Nice To Haves

• Coursework, projects, or internship experience related to space-based communications, wireless communications, or digital modem architecture.
• Academic exposure to signal processing concepts such as channelization, beamforming, synchronization, equalization, or coding.
• Awareness of radiation-tolerant or high-reliability design considerations.
• Exposure to formal verification, low-power methodologies, or FPGA emulation/prototyping through coursework or projects.
• Introductory knowledge of high-speed interface design and data movement architectures.

Responsibilities

• Support the design and delivery of ASIC IP blocks from specification through RTL release under the guidance of senior engineers.
• Assist in defining microarchitecture for digital signal-processing and control logic blocks.
• Participate in design trade studies involving throughput, latency, area, power, and schedule.
• Collaborate with systems, algorithm, and architecture teams to help translate communication requirements into hardware implementations.
• Work with verification, DFT, physical design, and firmware teams to support successful integration and tape-out readiness.
• Contribute to RTL development, test plans, and implementation reviews to help maintain high design quality.
• Help identify technical risks and bring them to the attention of the team early in the development cycle.
• Learn and apply standard processes in coding, review, and debug.
• Support post-silicon bring-up activities and assist in debugging lab or field issues.

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week)
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level