ASIC Engineering Technical Leader- STA

Cisco•San Jose, CA

9d•$210,600 - $350,800

About The Position

Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As a member of the team, you will contribute to defining innovative ASIC STA methodologies and creating robust flows essential for developing our complex chips. Your Impact: Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.

Requirements

Bachelor’s with 10 years of related experience, or Master’s with 5 years of related experience, or PhD with 2 years of related experience.
Prior experience with Integration for STA including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
Prior experience in developing timing constraints and signing off timing on blocks/sub system in advanced process nodes
Prior experience with timing closure with various timing ECO including transition, setup, hold, noise, xtalk, and power recovery.
Prior experience with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates.

Nice To Haves

Synthesis Tools: Synopsys. DC/DCG/FC
Formal Verification : Synopsys, Formality and Cadence LEC
Parasitic Extraction : Synopsys, Star-RCXT, Cadence Quantus
Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus
Scripting: TCL, Perl is required; Python is a plus

Responsibilities

Oversees the definition, architecture and design of high performance ASICs
Oversees all applications and code including methodology of reusable code
Oversees code creation and determines methodology behind coding
Consults for architecture and design decisions for complex areas
Drives design solutions across the business
Creates guidelines and standards
Creates innovative verification strategies
Oversees system level verification using test benches
Ensures culture of code reviews and postmortems
Architects and designs analog/mixed-signal circuits
Reviews complex IC designs and makes recommendations for improvements
Directs the mixed-signal team to define requirements, influences packaging and hardware team to ensure specifications are met
Oversees all physical design functions bringing technical expertise to highly complex scenarios
Interfaces with vendors and design leads on complex issues
Drives different technology design rules to develop innovative packages

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (for non-exempt employees)
flexible vacation time off program (for exempt employees)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay on top of their base salary (for sales roles)