ASIC Design Engineering Technical Leader

Cisco•San Jose, CA

10d•$183,800 - $303,100•Onsite

About The Position

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. This role requires being onsite in San Jose, CA at least 4 days/week.

Requirements

Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of ASIC experience.
Experience in high-performance RTL design using Verilog/SystemVerilog.
Experience with timing closure, power optimization, and clock gating techniques.
Experience with ASIC development flows including simulation, synthesis, and static timing analysis.
Strong debug, problem-solving, and cross-team collaboration skills.

Nice To Haves

Understanding of data center networking and storage architectures, including RDMA and NVMe-over-TCP.
Experience with ARM-based SoC architectures and protocols such as AXI, CHI, APB, and AHB, and ARM IP including CMN, GIC, and SMMU.
Design experience with high-speed interfaces and controllers including PCIe, Ethernet MAC, DDR/LPDDR, and DMA engines.
Experience integrating third-party IP into complex SoC environments.
Proficiency in engineering automation and scripting (Python, Perl, TCL, shell).
Experience with emulation, prototyping, or formal verification tools.

Responsibilities

Drive the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon.
Influence system architecture and key design decisions across complex SoC subsystems.
Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure.
Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets.
Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon.
Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges.
Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team.
Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.