FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX•Redmond, WA

4d•$125,000 - $175,000•Onsite

About The Position

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

Nice To Haves

ASIC/FPGA system integration experience
Proficiency in Python, C/C++, and Bash
Experience in designing DSP, digital communication system datapath blocks, and/or modem design
Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
Experience and understanding of AXI/AHB/APB protocols
Strong foundation in electrical engineering fundamentals
Experience debugging complex PCBs containing Microprocessors and FPGAs in the lab using equipment such as oscilloscopes and spectrum analyzers
Ability to work in a dynamic environment with changing needs and requirements
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
Demonstrated ability to work in a highly cross-functional role
Enjoys being challenged and learning new skills
Master’s in Electrical/Computer Engineering or related field

Responsibilities

Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/SystemVerilog
Optimize designs for power, performance and area
Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab
Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.
Collaborate with software engineers in developing production software for your designs