ASIC Design Verification Engineering Technical Leader
About The Position
This role is within the Common Hardware Group (CHG) at Cisco, which develops innovative hardware platforms for the AI era, powering Cisco’s core Switching, Routing, and Wireless products. The team is responsible for full product development from design to qualification to production. The position involves participating in ASIC design verification for high-end switching products, leading the architecture, development, and maintenance of Design Verification (DV) environments, and developing simulation models, test plans, and coverage strategies. The role also includes constructing testbench components, collaborating with cross-functional teams for debugging, ensuring verification coverage, contributing to chip architecture, and mentoring junior engineers.
Requirements
- Bachelor’s degree in Electrical or Computer engineering and 10+ years of ASIC Design and Verification experience or Master’s degree in Electrical or Computer engineering and 8+ years of ASIC Design and Verification experience.
- Experience with ASIC design and verification processes (with System Verilog), debugging, methodology, and tools.
- Experience in leading the verification methodology (in UVM) of clusters/subsystems or full chip level for ASIC.
Nice To Haves
- Prior people management experience.
- Dashboard management for regression, coverage, test list completion and other DV statistics.
- Post-silicon lab bring-up experience.
- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS
- Experience with Linux, C/C++, and/or Python/Perl.
- Experience in Networking.
Responsibilities
- Participate in the ASIC design verification for Cisco high-end switching products.
- Lead, architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.
- Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.
- Construct testbenches components like scoreboard, agents, sequencers, and monitors.
- Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration and customer failures.
- Ensure comprehensive verification coverage through code and functional coverage implementation and review.
- Participate in and contribute to chip architecture definition and discussions.
- Mentor junior engineers on performing project tasks and problem solving.
Benefits
- medical insurance
- dental insurance
- vision insurance
- 401(k) plan with a Cisco matching contribution
- paid parental leave
- short-term disability coverage
- long-term disability coverage
- basic life insurance
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt employees)
- flexible vacation time off program (exempt employees)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
- performance-based incentive pay (for sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
