ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems
About The Position
Qualcomm Technologies, Inc. is seeking ASIC Design Engineers to contribute to the architecture, microarchitecture, design, and deployment of next-generation SoC interconnects, cache and memory subsystems, and high-speed DDR memory controllers. These systems support products including smartphones, PCs, XR devices, and automotive platforms. The engineer will work with architecture, verification, physical design, and software teams to develop high-performance, power-efficient silicon solutions. The role involves defining microarchitecture and design specifications, implementing and validating RTL, optimizing designs, supporting implementation and integration, and investigating issues through pre-silicon and post-silicon development.
Requirements
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 0–4+ years of industry experience or relevant academic experience in ASIC/SoC design.
- Experience or coursework in Verilog and/or SystemVerilog RTL design, computer architecture, ASIC design methodologies, digital logic design, and C, C++, and/or Python programming.
- Strong analytical and problem-solving skills.
- Excellent communication and collaboration skills.
- Minimum qualification: Bachelor's degree in Science, Engineering, or a related field.
Nice To Haves
- Experience or knowledge of SoC interconnects and on-chip communication fabrics.
- Experience or knowledge of cache and memory subsystem design.
- Experience or knowledge of DDR/LPDDR memory controller architecture and design.
- Experience or knowledge of ARM or x86 processor architectures and bus protocols.
- RTL development experience for CPUs, cache controllers, or memory controllers.
- Knowledge of low-power design methodologies.
- Knowledge of functional verification and coverage-driven verification techniques.
- Experience with Synopsys synthesis tools and ASIC implementation flows.
- Experience with timing closure, physical design support, and power optimization.
- Experience with silicon bring-up and post-silicon debug.
Responsibilities
- Develop microarchitecture definitions and design specifications for complex SoC subsystems.
- Design, implement, and validate RTL for SoC interconnects, cache controllers, memory subsystems, and DDR memory controller components.
- Collaborate with system architects to evaluate the hardware feasibility of new features, algorithms, and performance requirements.
- Optimize designs for performance, power, area, timing, and scalability.
- Work with verification teams to develop test plans, review coverage, debug issues, and achieve design quality goals.
- Support synthesis, timing closure, power analysis, gate-level simulations, and physical design activities.
- Participate in system-level integration and debugging throughout the product development cycle.
- Investigate and resolve pre-silicon and post-silicon issues.
- Contribute to C/C++ modeling, design methodologies, and process improvements that enhance engineering productivity and design quality.
- Collaborate across cross-functional teams to deliver silicon for production.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants, except for employees on sales-incentive plans.
- Competitive benefits package designed to support employees at work, at home, and at play.
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
