Design Verification Engineer - Fabric Interconnect

Microsoft • Raleigh, NC

1d

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops the infrastructure and foundational technologies that power Microsoft’s online businesses and Azure platform. Within SCHIE, the Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages computer chips, including Azure Cobalt. Its Verification & Validation team supports the quality, delivery, scale, and sustainability of Microsoft cloud hardware.

The Design Verification Engineer – Fabric Interconnect will contribute to integration-level verification of Fabric Top, including coherency, PCIe/CXL traffic, and configuration access traffic. The role involves collaborating with partner IP, SOC, and VIP teams to define verification strategies and test plans; building and running verification environments; debugging simulations; and improving verification efficiency using automation, formal methods, and generative AI. The engineer will also coach and mentor others in areas of expertise.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or bachelor's degree in one of those fields and at least 2 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Provide proof of citizenship, U.S. residency, or other protected status as required to assess eligibility for access to export-controlled information; citizenship will be verified with a valid passport, with other applicable documentation accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Demonstrated experience leading verification of designs that use Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols.
• Demonstrated experience in one or more of fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, or protocol bridges.
• Experience driving IP verification across multiple product cycles from definition to silicon, including writing IP/block or subsystem-level test plans, developing tests, debugging failures, and completing coverage signoff.
• Experience creating, maintaining, or integrating test benches, checkers, and stimulus using UVM, SystemVerilog Test Bench (SVTB), and optionally Python-based post-processing checks.
• Aptitude for writing scripts or software with industry-standard languages such as Python.
• Experience applying generative AI to day-to-day tasks.

Responsibilities

• Own aspects of integration-level verification of Fabric Top across coherency (such as CHI), PCIe/CXL traffic, and configuration access traffic.
• Learn the design and work with partner IP, SOC, and VIP teams to define verification strategies and test plans.
• Develop UVM/SystemVerilog-based integration-level verification environments, and run and debug simulations to drive quality.
• Use automation, formal-based methods, and AI-based approaches as additional verification tools.
• Innovate to improve verification efficiency through methodologies or tools.
• Apply generative AI solutions to verification work.
• Coach and mentor others in areas of expertise.
• Demonstrate Microsoft core values, including customer focus, adaptability, collaboration, growth mindset, drive for results, influence for impact, judgment, and diversity and inclusion.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level