APTM Yield Analysis/Device Engineer

Intel•Rio Rancho, NM

3d•Hybrid

About The Position

Intel is seeking an APTM Yield Analysis/Device Engineer for its Advanced Packaging Technology and Manufacturing (APTM) Yield Group. The role drives yield and defect improvement across Intel’s advanced packaging portfolio and helps transition packaging technologies from development into high-volume manufacturing. Based in the Albuquerque, New Mexico area, the engineer analyzes large, multidimensional factory datasets to identify opportunities to optimize manufacturing processes, test content, and inline metrologies. The position also serves as a technical advisor, setting engineering priorities, leading cross-functional problem solving, and influencing the technology yield roadmap. The role includes leading a small group of engineers, directly or indirectly, to run experiments, resolve nonstandard yield events, and support technology transfers to high-volume manufacturing. The engineer reports on yield and device health to upstream and downstream partners and establishes action plans to achieve high yield. The position is eligible for Intel’s hybrid work model, with time split between the assigned Intel site and off-site work.

Requirements

Bachelor's degree in Materials Science, Mechanical Engineering, Computer Science, Information Systems, Chemical Engineering, Electrical Engineering, Chemistry, Physics, or a related technical discipline, and 5 or more years of semiconductor industry experience; or
Master's degree in a matching discipline and 3 or more years of semiconductor industry experience; or
PhD in a matching discipline and 1 or more years of semiconductor industry experience.
Ability to lead, guide, and collaborate across organizational boundaries.
Ability to adapt to changing priorities, new technical fields of study, and fluctuating business demands.
Ability to work with minimal direct oversight, prioritize critical-path items, and resolve complex, unstructured technical issues.
Ability to deliver concise, high-impact technical presentations to influence decision-making among diverse groups.

Nice To Haves

2 or more years of experience using JMP, Python, or alternative data engineering software for statistical data analysis.
2 or more years of experience applying statistical analysis to high-volume manufacturing data.
2 or more years of experience using structured technical problem-solving methodologies, such as Model-Based Problem Solving.
2 or more years of experience linking product design, circuit architecture, or DFT to yield analysis.
2 or more years of experience working directly with inline defect metrology equipment or defect classification systems.

Responsibilities

Extract insights from structured and unstructured factory datasets using statistical methods, machine learning, and tools such as JMP or Python.
Correlate electrical and physical failure mechanisms using knowledge of Failure Analysis (FIFA), Design for Test (DFT), Sort/Test, and Integration/Process flows.
Manage inline defect metrologies, evaluate detection capabilities, and drive inline defect reduction programs across the factory.
Lead a small group of engineers, directly or indirectly, to execute experiments, resolve nonstandard yield events, and support technology transfers to high-volume manufacturing.
Deliver detailed technical reports on yield and device health to upstream and downstream partners, and establish action plans to achieve best-in-class yield.
Set engineering priorities and lead cross-functional problem-solving initiatives to influence the technology yield roadmap.