APTM Yield Analysis/Device Engineer

Intel Corporation•Rio Rancho, NM

5d•$122,440 - $232,190•Hybrid

About The Position

Intel is seeking an APTM Yield Analysis/Device Engineer for its Advanced Packaging Technology and Manufacturing Yield Group. The role supports technology development, transfers, and manufacturing ramps, helping improve yield and reduce defects across Intel’s advanced packaging portfolio. The engineer analyzes large, multidimensional datasets to identify opportunities to optimize manufacturing processes, test content, and inline metrologies, and helps guide engineering priorities and the technology yield roadmap. The position involves correlating electrical and physical failure mechanisms, optimizing defect detection and reduction, and leading engineering work to investigate yield events and support technology transfers into high-volume manufacturing. It also requires communicating technical findings and action plans to upstream and downstream partners. The role is eligible for Intel’s hybrid work model, splitting time between an assigned Intel site and off-site work.

Requirements

Bachelor's degree in Materials Science, Mechanical Engineering, Computer Science, Information Systems, Chemical Engineering, Electrical Engineering, Chemistry, Physics, or a related technical discipline, plus 5 or more years of semiconductor industry experience; or a master's degree in a matching discipline plus 3 or more years; or a PhD in a matching discipline plus 1 or more years.
Ability to lead, guide, and collaborate across diverse organizational boundaries.
Ability to adapt to changing priorities, new technical fields of study, and changing business demands.
Ability to work with minimal direct oversight, prioritize critical-path items, and resolve complex, unstructured technical issues.
Ability to deliver concise, high-impact technical presentations to influence decision-making among diverse groups at all levels.

Nice To Haves

2 or more years of experience with JMP, Python, or alternative data engineering software for statistical data analysis.
2 or more years of experience applying statistical analysis to high-volume manufacturing data.
2 or more years of experience using structured technical problem-solving methodologies, such as Model-Based Problem Solving.
2 or more years of experience linking product design, circuit architecture, or DFT to yield analysis.
2 or more years of experience working directly with inline defect metrology equipment or defect classification systems.

Responsibilities

Extract insights from structured and unstructured factory datasets using statistical methods, machine learning, and tools such as JMP or Python.
Correlate electrical and physical failure mechanisms using knowledge of Failure Analysis (FIFA), Design for Test (DFT), Sort/Test, and Integration/Process flows.
Manage inline defect metrologies, evaluate their detection capabilities, and drive inline defect reduction programs across the factory.
Lead a small group of engineers, directly or indirectly, to execute experiments, resolve nonstandard yield events, and support smooth technology transfers to High-Volume Manufacturing (HVM).
Deliver technical reports on yield and device health to upstream and downstream partners, and establish action plans to achieve high yield levels.
Set engineering priorities and lead cross-functional problem-solving initiatives that influence the technology yield roadmap.