Graduate - Analog Mixed-Signal Design Verification Engineer

Infineon•Andover, MA

1d•$75,000 - $93,000•Onsite

About The Position

Infineon Technologies is seeking Graduate Analog Mixed-Signal Design Verification Engineers to join their team. This role is part of the Graduate Programs or can be a first full-time role, providing tools, trust, and challenges for rapid growth. The company is focused on creating tiny chips and big careers, enabling game-changing solutions for green and efficient energy, clean and safe mobility, and smart and secure IoT. Infineon is committed to diversity and inclusion, offering a workplace built on trust, openness, respect, and equal opportunity.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or a related field with an expected graduation date of Spring 2026, Fall 2026, or Spring 2027.
Experience with analog and mixed-signal verification concepts, testbench creation, and debug practices.
Experience with Verilog-AMS and SystemVerilog and familiarity with mixed-signal modeling approaches.
Good understanding of analog design techniques.
Understanding of hierarchy configurations and mixed-signal netlisting flows.
US citizen or green card holder: This position requires access to documentation that is controlled by the export laws of the United States. Candidates are required to provide proof of either US citizenship, Permanent US residency, or classification as a protected individual as defined in 8USC 1324b(a)(3).

Nice To Haves

Exposure to Cadence Virtuoso, Spectre, ADE Explorer/Assembler, vManager, and Xcelium.
Experience with Python, TCL, or MATLAB for automation, data analysis, or flow enablement.
Strong analytical, organizational, and communication skills with ability to collaborate across design and verification teams.

Responsibilities

Develop verification plans per device specifications and requirements to ensure coverage of analog and mixed-signal design intent.
Generate and maintain Verilog-AMS, SystemVerilog, and mixed-signal behavioral models to support simulation and verification workflows.
Develop testbenches, simulation environments, and regression flows for mixed-signal verification.
Create and execute mixed-signal simulation flows to validate device-level and system-level behavior across operating conditions.
Evaluate behavior under nominal and corner conditions to ensure design robustness and performance compliance.
Implement fault-injection and stress scenarios to validate error handling and edge-case behavior.
Run, debug, and maintain regression suites using tools such as Cadence Virtuoso, Cadence vManager, ADE Explorer/Assembler, Spectre, and Xcelium.