Analog Design, Sr Architect - 18618

Synopsys•Sunnyvale, CA

10d•Onsite

About The Position

Synopsys is seeking a Principal-level analog design leader to shape the architecture and implementation of silicon-proven analog macros for high-speed SerDes IP. The role operates at the architecture and system boundary, translating standards and product requirements into robust, scalable circuit and layout implementations. It calls for technical leadership across teams, sound power, area, and performance trade-offs, disciplined verification, and clear communication with internal stakeholders and customers. The successful candidate will lead macro-level architecture, design, and implementation across SerDes transmit, receive, and clock paths. They will set specifications and design targets, guide reusable circuit platforms, coordinate technical execution across sub-block owners, and work with digital teams on calibration, adaptation, and control interfaces. The role also provides oversight of verification, behavioral modeling, silicon correlation, physical layout, characterization, and test strategy, while mentoring engineers and improving team methodologies. The role is part of a multidisciplinary team of analog, digital, and mixed-signal engineers developing high-performance, reliable, and scalable SerDes IP. It is based in Sunnyvale, California, and is not remote eligible. The position may be eligible for an annual bonus, equity, and other discretionary bonuses, alongside comprehensive health, wellness, and financial benefits. Compensation depends on job-related factors; the listed U.S. base salary range is $0–$0.

Requirements

PhD with 10+ years, or MSc with 12+ years, of SerDes or high-speed analog design experience and multiple silicon successes.
Demonstrated ability to lead macro-level architecture and deliver complex analog IP through tapeout and silicon validation.
Deep transistor-level design expertise and strong CMOS and FinFET fundamentals.
Silicon-proven experience implementing circuits for TX, RX, and clock paths within SerDes architectures.
In-depth knowledge of SerDes sub-circuits, including equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
Advanced skills guiding FinFET CMOS layouts to minimize parasitics and local device mismatches.
Awareness of ESD and reliability issues, including circuit techniques and layout strategies.
Proficiency with EDA tools for schematic entry, physical layout, and design verification.
Experience with SPICE simulators for detailed circuit analysis.
Familiarity with analog behavioral modeling and simulation control using Verilog-A.
Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.
Clear potential to lead a team in the near future as the team grows.

Responsibilities

Own macro-level architecture, design, and implementation of critical SerDes analog circuits across TX, RX, and clock paths.
Translate SerDes standards and system architecture into analog specifications, budgets, and targets for jitter, noise, linearity, settling, latency, power, and area.
Drive top-level architecture trade-offs and define scalable circuit platforms reusable across product variants and process nodes.
Lead and track technical execution across sub-block owners, identify risks, remove blockers, and align work to schedules and product goals.
Define interfaces between analog macros and digital calibration, adaptation, and control; partner with RTL and firmware teams to co-define algorithms and observability hooks.
Define and enforce verification strategies using SPICE and simulator capabilities, including corner and Monte Carlo analysis, aging, mismatch, noise, transient jitter, PVT sweeps, and reliability checks.
Promote Verilog-A behavioral modeling to accelerate system validation and improve correlation between block- and top-level results.
Drive silicon correlation plans by defining measurements, mapping results to simulations, and applying findings to design improvements.
Provide technical oversight of physical layout to minimize parasitics, coupling, device stress, and sensitivity to process variation, and address reliability and ESD early.
Guide FinFET layout strategies for mismatch, symmetry, routing, shielding, EM and IR, and high-speed interconnect integrity.
Present architecture rationale, simulation results, and risk assessments in peer and customer reviews, answering technical questions with data-backed clarity.
Consult on electrical characterization and test strategy for SerDes IP macros, influencing DFT and bring-up hooks and lab-debug workflows.
Mentor junior and mid-level engineers and set expectations for design quality, documentation, and review rigor.
Contribute reusable collateral, methodology improvements, and onboarding practices as the organization scales.