Intern- Analog Design

Infineon•Austin, TX
•$21 - $36

About The Position

The Analog Design Intern supports analog and digital design and verification of mixed-signal IP using Cadence tools across various SoC scenarios. The role includes developing and running mixed-signal testbenches and simulations for digital multiphase buck controllers, integrated power stages, and voltage regulator designs, as well as functional verification of power management circuits. The intern conducts bench-level silicon evaluations to characterize IC performance, document results, and prepare validation reports. The role also develops scalable, reusable constrained-random testbenches using SystemVerilog and UVM. The intern collaborates with analog and digital IC design experts and cross-functional teams to improve unit architecture performance and develop next-generation IP, while building analog and mixed-signal design skills through hands-on contributions.

Requirements

  • Currently enrolled in or recently graduated from a Bachelor's or Master's program in Electrical Engineering or a closely related field.
  • Hands-on experience with Cadence tools for schematic creation, netlist generation, and simulation execution in analog or mixed-signal environments.
  • Familiarity with hardware verification languages, including SystemVerilog and UVM, for constrained-random testbench development.
  • Exposure to lab test equipment such as oscilloscopes and digital multimeters for hardware bring-up and IC characterization.
  • Experience with Python programming and Unix/Linux shell commands for scripting, automation, and simulation workflow support.
  • Awareness of communication protocols such as PMBus, I2C, UART, or SPI relevant to microcontroller-based testbench and firmware co-verification.
  • Strong written and verbal communication skills and the ability to contribute effectively within cross-functional engineering teams.

Responsibilities

  • Assist with analog and digital design and verification of mixed-signal IP using Cadence tools across SoC scenarios.
  • Create mixed-signal testbenches and execute simulations for digital multiphase buck controllers, integrated power stages, and voltage regulator designs.
  • Perform functional verification of power management circuits, including digital multiphase buck controllers and integrated power stages.
  • Conduct bench-level silicon evaluation to characterize IC performance, document results, and prepare structured validation reports.
  • Develop scalable and reusable constrained-random testbenches using SystemVerilog and UVM object-oriented methodologies.
  • Collaborate with analog and digital IC design experts and cross-functional teams to improve unit architecture performance and develop next-generation IP.
  • Build analog and mixed-signal design competencies by contributing to next-generation IP and exploring product design solutions.
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