The Analog Design Intern supports analog and digital design and verification of mixed-signal IP using Cadence tools across various SoC scenarios. The role includes developing and running mixed-signal testbenches and simulations for digital multiphase buck controllers, integrated power stages, and voltage regulator designs, as well as functional verification of power management circuits. The intern conducts bench-level silicon evaluations to characterize IC performance, document results, and prepare validation reports. The role also develops scalable, reusable constrained-random testbenches using SystemVerilog and UVM. The intern collaborates with analog and digital IC design experts and cross-functional teams to improve unit architecture performance and develop next-generation IP, while building analog and mixed-signal design skills through hands-on contributions.
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Job Type
Full-time
Career Level
Intern