Vice President of ASIC Engineering

Architect Labs • Palo Alto, CA

12d

About The Position

Architect Labs is a frontier AI lab for custom silicon, partnering with frontier labs, clouds and neoclouds, physical AI companies, and advanced fabs to tape out custom chips for next-generation AI workloads. The team aims to shorten end-to-end software-to-silicon timelines and maximize intelligence per watt and per dollar.

The Vice President of ASIC Engineering will own ASIC methodology and end-to-end delivery of ambitious AI compute silicon, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. The role will build a faster, AI-native chip-development flow using automation, intelligent agents, and data-driven feedback loops to accelerate design iteration, verification, closure, and engineering productivity. The leader will build and lead a world-class team, set a high bar for performance, power, area (PPA), and silicon quality, and personally drive consequential technical and execution decisions.

Requirements

• Directly led multiple complex, production-volume ASIC or SoC programs through successful tapeout.
• Deep expertise spanning RTL, functional verification, synthesis, timing closure, physical implementation, DFT, signoff, and silicon bring-up.
• Track record of transforming design flows through automation, ML/AI-assisted EDA, verification productivity, or scalable engineering infrastructure.
• Demonstrated ability to deliver demanding programs with strong first-silicon outcomes and disciplined engineering tradeoffs.
• Record of recruiting, developing, and leading world-class silicon engineers and technical leaders.
• Hands-on technical leadership and the credibility to resolve difficult cross-functional engineering problems.

Nice To Haves

• Experience with advanced process nodes.

Responsibilities

• Own ASIC methodology and end-to-end delivery of AI compute silicon, from microarchitecture and RTL through verification, physical design, signoff, and tapeout.
• Build an AI-native chip-development flow using automation, intelligent agents, and data-driven feedback loops to accelerate design iteration, verification, closure, and engineering productivity.
• Lead and develop a world-class silicon engineering team.
• Set a high bar for PPA and silicon quality.
• Personally drive consequential technical and execution decisions and resolve difficult cross-functional engineering problems.
• Build scalable engineering processes.

Benefits

• Competitive compensation
• Meaningful equity
• Ownership of critical silicon programs
• Opportunity to build a world-class ASIC organization at the frontier of computing

What This Job Offers

• Job Type: Full-time
• Career Level: Executive
• Education Level: No Education Listed