Vice President of ASIC Engineering

Architect Labs•Palo Alto, CA

11d

About The Position

Architect Labs is a frontier AI lab focused on custom silicon. It partners with frontier labs, clouds and neoclouds, physical AI companies, and advanced fabs to tape out custom chips co-designed for next-generation AI workloads. Its goal is to shorten end-to-end software-to-silicon timelines and maximize intelligence per watt and per dollar. The team spans silicon, systems, software, and frontier AI, with experience at frontier AI labs and on complex SoCs. The Vice President of ASIC Engineering will own ASIC methodology and the end-to-end delivery of ambitious AI compute silicon, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. The role will develop a faster, AI-native chip-development flow using automation, intelligent agents, and data-driven feedback loops to accelerate design iteration, verification, closure, and engineering productivity. This leader will build and lead a world-class team, set a high bar for PPA and silicon quality, and personally drive consequential technical and execution decisions. Architect Labs offers competitive compensation and meaningful equity, ownership of critical silicon programs, and the opportunity to build a world-class ASIC organization at the frontier of computing.

Requirements

Directly led multiple complex, production-volume ASIC or SoC programs to tapeout; experience at advanced process nodes is preferred.
Deep expertise across RTL, functional verification, synthesis, timing closure, physical implementation, DFT, signoff, and silicon bring-up.
Track record of transforming design flows through automation, ML/AI-assisted EDA, verification productivity, or scalable engineering infrastructure.
Demonstrated ability to deliver demanding programs with strong first-silicon outcomes and disciplined engineering tradeoffs.
Record of recruiting, developing, and leading world-class silicon engineers and technical leaders.
Hands-on technical credibility to resolve difficult cross-functional engineering problems while building processes that scale.

Nice To Haves

Experience leading programs at advanced process nodes.

Responsibilities

Own ASIC methodology and end-to-end delivery of AI compute silicon, from microarchitecture and RTL through verification, physical design, signoff, and tapeout.
Build a faster, AI-native chip-development flow using automation, intelligent agents, and data-driven feedback loops.
Accelerate design iteration, verification, closure, and engineering productivity.
Lead and develop a world-class silicon engineering team.
Set a high bar for PPA and silicon quality.
Personally drive consequential technical decisions, execution decisions, and difficult cross-functional engineering problems.
Build scalable processes and an ASIC organization.