Strategic Partnerships Manager, Memory

Meta•Sunnyvale, CA

About The Position

The Memory Strategic Technology Lead is a Strategic Partnerships Manager, Memory role within Reality Labs Global Strategic Sourcing (GSM), responsible for driving and program-managing memory technology strategy across the full RL product portfolio — including AR glasses, VR headsets, smartwatches, and AI wearables. This person serves as the primary technical and programmatic bridge between Memory Sourcing, Silicon Architecture, Product Engineering, and our supplier base, translating product roadmaps and technology transitions into actionable sourcing strategies that secure supply, reduce cost, and mitigate risk. You will own and program-manage the memory technology roadmap from a sourcing perspective — evaluating emerging DRAM, NAND, NOR, and PSRAM technologies, driving supplier qualification and development, and shaping Meta's position in industry standards bodies. This role requires semiconductor domain expertise, cross-functional program management skills, and the commercial acumen to influence multi-year supply agreements and pricing structures worth hundreds of millions of dollars annually.

Requirements

Bachelor's degree in Electrical Engineering, Materials Science, Physics, or related technical field
10+ years of experience in semiconductor memory technology, memory product engineering, technical program management, or technical sourcing/supply chain roles with memory domain expertise
Working knowledge of DRAM (LPDDR4x, LPDDR5/5x), NAND (eMMC, UFS), NOR flash, and PSRAM technologies — including process nodes, die architectures, and packaging
Experience with memory qualification processes, including JEDEC standards, PVL/PRQ flows, and reliability testing
Demonstrated ability to translate complex technical information into business decisions for non-technical stakeholders, with a track record of leading cross-functional programs from definition through execution
Experience engaging with memory suppliers at a technical level — reviewing datasheets, evaluating die specifications, and assessing supplier roadmaps
Analytical skills with experience in cost modeling, density/power/performance trade-off analysis, and total cost of ownership frameworks
Experience in technical program management — including program planning, milestone tracking, dependency management, cross-functional stakeholder alignment, and executive communication

Nice To Haves

Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies
Master's degree or PhD in Electrical Engineering, Materials Science, or Semiconductor Physics, MBA or PMP certification is a plus
Direct experience with mobile/consumer memory products (ePOP, MCP, uPOP, SiP) — not just datacenter/server memory
Experience with advanced packaging technologies: fan-out wafer-level packaging, 2.5D/3D integration, in-package memory (IPM), or known-good-die (KGD) sourcing
Prior experience at a memory semiconductor company (Micron, SK Hynix, Samsung, Kioxia) or in a memory-focused sourcing role at a consumer electronics OEM
Familiarity with JEDEC standards development process and participation in industry working groups
Experience supporting LTA or supply agreement negotiations with technical analysis and cost modeling
Understanding of export control and trade compliance considerations as they apply to semiconductor sourcing (e.g., Entity List, DoD 1260H implications)
Experience with NOR flash and PSRAM markets — including low-density specialty memory for IoT/wearable applications
Track record of driving multi-source qualification to reduce supplier concentration risk
Proven experience as a Technical Program Manager (TPM) in semiconductor, hardware, or consumer electronics organizations — with demonstrated ability to lead cross-functional programs spanning engineering, supply chain, and product teams
Experience building and presenting executive-level program updates, risk registers, and technology readiness assessments to VP/Director-level stakeholders

Responsibilities

Own the RL memory technology roadmap from a sourcing perspective, spanning LPDDR4x/LP5x, eMMC, UFS, ePOP, uPOP, IPM, NOR flash, and PSRAM across all RL product lines
Define and drive technology qualification strategy for new memory products — including die-level evaluation, wafer vs. packaged sourcing models, and multi-source qualification to eliminate sole-source risk
Lead and program-manage technical engagement with memory suppliers (Micron, SK Hynix, Samsung, CXMT, and packaging partners) on product roadmaps, die specifications, package architecture, and advanced packaging technologies (IPM, KGD, wafer-level)
Evaluate and recommend memory density transitions (e.g., 2GB to 3GB to 4GB DRAM, 32GB to 64GB to 128GB NAND) based on cost, power, performance, and supply availability trade-offs
Partner with Silicon Architecture to translate system-level requirements (bandwidth, peak power, package dimensions, thermal constraints) into supplier specifications and qualification plans
Develop and maintain technical scorecards for supplier capability assessment — covering process node, die size, power efficiency, package technology, and reliability
Represent RL Memory Sourcing in NPI milestone reviews, SPOR governance forums, and cross-functional design reviews — driving alignment across engineering, sourcing, and product leadership to ensure sourcing requirements are embedded in product decisions
Track industry technology trends through analyst reports (TechInsights, Counterpoint, CRC/CCI), supplier roadmap disclosures, and JEDEC standards activity to inform forward-looking sourcing strategy
Support LTA negotiations with technical analysis — including cost modeling at the die/wafer level, density premium benchmarking, and technology migration impact assessment
Drive supplier development for emerging memory technologies (IPM2, UFS for wearables, custom DRAM packaging) in partnership with advanced packaging and silicon teams
Program-manage NPI qualification timelines, sample procurement, and PVL coordination with Qualcomm, MediaTek, and internal hardware engineering teams — owning end-to-end schedules, tracking dependencies, and escalating risks to leadership
Provide technical input on trade compliance and supply chain geo-diversification decisions as they relate to memory semiconductor sourcing
Develop and maintain program trackers, dashboards, and executive briefing materials that provide visibility into memory technology readiness, qualification status, and sourcing risk across the RL portfolio
Drive structured decision-making across stakeholders by facilitating technology trade-off reviews, risk assessments, and go/no-go qualification gates