Staff Technical Program Manager, ASIC

Neurophos • Austin, TX

19h • Onsite

About The Position

The Electronic IC (EIC) is the high-speed mixed-signal ASIC at the heart of our optical compute engine. It drives, reads out, and controls our photonic hardware and connects it to the rest of the system. We are looking for an experienced hardware TPM to drive the EIC program end-to-end: from architecture convergence with our chip architects, through design, verification, physical design, and tapeout at a leading-edge foundry, into post-silicon bring-up and system integration. You will be the connective tissue between the architecture team, digital/analog/mixed-signal design, DV, physical design, packaging, photonics, and platform hardware — and the single source of truth for EIC schedule, risk, and readiness. This is a first-silicon program at a fast-moving startup: you will define the process where none exists, and you'll be judged on working silicon. We develop silicon the AI-first way. AI agents and LLM tooling are embedded in how we write specs, track requirements, generate and review code, close verification, and run the program itself. You'll drive it: building an AI-augmented program machine.

Requirements

• BS in Electrical/Computer Engineering or equivalent (MS preferred).
• 10+ years in ASIC/SoC development , as a TPM/EPM (or equivalent lead role) on complex silicon programs.
• 2+ complete silicon programs taken from architecture/specification through tapeout at a reputable foundry , with at least one carried through post-silicon bring-up to production or system integration.
• Working fluency across the full silicon lifecycle: architecture, front-end design, verification, FPGA/emulation, physical design, DFT, signoff, package and substrate design, foundry manufacturing, bring-up, ATE, and reliability/qualification.
• Direct experience managing foundry, IP vendor, OSAT, and design-services relationships, including tapeout logistics and mask releases.
• Enough technical depth to communicate credibly with engineers across the design stack, pressure-test schedules, and understand the technical substance of the risks you are driving.
• Demonstrated cross-functional leadership: aligning multiple engineering teams and external partners without direct authority, and communicating clearly from lab bench to boardroom.
• Hands-on command of program tooling (Jira or equivalent, dependency/schedule tracking, dashboards and checklists you build yourself).
• Fluent, daily use of AI tools in your own program work and an automate-first instinct, with judgment about where AI output needs human verification.

Nice To Haves

• Mixed-signal or high-speed analog program experience (SerDes, data converters, drivers/TIAs) or exposure to optical transceivers / silicon photonics.
• Advanced packaging experience: 2.5D/3D integration, interposers, CoWoS, hybrid bonding.
• First-silicon or startup experience.
• Familiar with building a program process from scratch on a small team.
• A prior hands-on background in design, DV, or physical design before moving into program management.
• Familiarity with formal gate-review frameworks (PDR/CDR) and requirements management.
• TPM experience on ML accelerator or data-center hardware programs (GPU, TPU, custom accelerators, networking).
• Hands-on experience deploying AI-assisted EDA, verification, or agentic engineering workflows on a real silicon program.

Responsibilities

• Drive the end-to-end EIC program: integrated schedule, milestones, dependency map, staffing outlook, and risk register from architecture through tapeout, bring-up, and production readiness.
• Champion the AI-first development flow: deploy AI/LLM tooling across spec and requirements management, schedule and dependency tracking, risk registers, status reporting, and documentation.
• Partner with the architecture team to converge the EIC specification.
• Drive spec and design reviews, decision logs, freeze criteria, and change control to ensure downstream execution starts from a stable baseline.
• Drive execution across RTL, DV, analog/mixed-signal, DFT, and physical design teams, and coordinate external partners: IP vendors, EDA vendors, design services, foundry, and OSAT.
• Partner with design and DV leads to adopt AI-assisted design, verification, and debug-triage flows where they cut schedule without compromising signoff quality.
• Build and drive the tapeout readiness checklist: verification closure, timing/physical/electrical signoff, DRC/LVS, mask release.
• Run the tapeout decision process with engineering leadership.
• Manage the foundry engagement day-to-day: shuttle and full-mask schedules, PDK/deck updates, wafer starts, and delivery tracking.
• Drive post-tapeout execution: bring-up plan and lab readiness, package/assembly and OSAT coordination, ATE and bench test planning, silicon debug triage, errata tracking, and respin scoping if needed.
• Track cross-domain dependencies between the EIC and photonic IC, package/substrate, board, firmware, and software teams; surface risks early and drive mitigation to closure.
• Run the program rhythm: cross-functional syncs, escalation paths, phase-gate reviews (PDR/CDR/tapeout/bring-up), and crisp status reporting to the executive team.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching and stock option opportunities.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior