About The Position

Google software engineers develop technologies that help users connect, explore, and interact with information at massive scale. This role is part of the team developing software for Google’s custom accelerators, including TPUs for machine learning and VCUs for video encoding and decoding. The engineer will develop C++ code to control and monitor these ASICs and define APIs used by the broader software stack to build large-scale deployments. The work includes handling interrupts, DMAs, and other hardware-centric features, as well as participating in initial debugging and bring-up of new ASICs. The team also maintains simulation models that enable pre-silicon software development and collaborates with external vendors and internal chip design, system software, ML supercomputer, compiler, and system test teams. The role is part of Google’s AI and Infrastructure organization, which delivers AI and infrastructure capabilities at scale for Google users and customers. Individual pay is determined by job-related skills, experience, and relevant education or training. The listed US compensation is $207,000–$300,000, plus a 20% bonus target, equity, and benefits.

Requirements

  • Bachelor’s degree or equivalent practical experience.
  • 8 years of experience in software development.
  • 5 years of experience working with embedded operating systems.
  • 3 years of experience with software design and architecture.
  • Experience in C, C++, and embedded systems.

Nice To Haves

  • Master’s degree or PhD in Engineering, Computer Science, or a related technical field.
  • 8 years of experience with data structures and algorithms.
  • 3 years of experience working in a complex, matrixed organization involving cross-functional or cross-business projects.
  • Experience in embedded C/C++, embedded software development, hardware/software code design at the chip level, multithreaded designs, machine learning, and video encoding/decoding.

Responsibilities

  • Develop firmware for ASIC power-on and reset, low-level hardware initialization, security, and virtualization of ASICs across multiple processes and virtual machines.
  • Support trusted firmware and key management, and protect user data and privacy through security technologies such as confidential computing.
  • Develop tools to update and debug ASIC firmware and enable chip bring-up and hardware debugging.
  • Collaborate with hardware design and development teams on hardware/software interface code design.
  • Build functional and cycle-level simulators that accurately model custom accelerator ASICs, along with tools and infrastructure for ASIC design verification, tapeout, and bring-up.
  • Develop embedded CPU simulators as part of the full system simulator.

Benefits

  • 20% bonus target
  • Equity
  • Benefits
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