Staff IC Packaging Engineer - Mechanical Simulation

Qualcomm • San Diego, CA

2d • $154,000 - $231,000

About The Position

This position is part of Qualcomm’s Integrated Circuits (IC) package engineering process team. This role offers a unique opportunity to impact Qualcomm's current/future chipsets using FEA expertise, working closely with design, new product introduction (NPI) and Chip-Package Interaction (CPI) teams by providing mechanical simulation support for current HVM and advanced packaging technologies. This role requires development of mechanical FEA models (preferably using ANSYS APDL and Workbench), maintain APDL macros/workflows, establish FEA methodologies/BKM for test correlation, material characterization, and performing stress/mechanical analysis for IC package designs and failure prediction. Job responsibilities include but are not limited to: Warpage/Stress analysis, Solder joint reliability (SJR) prediction, package assembly process simulation, and chip package interaction (CPI) analysis. The candidate must be capable of utilizing advanced Finite Element Analysis (FEA) techniques (sub-modeling approach, contact analysis, non-linear analysis), and test procedures for material characterization/testing. Candidate should also understand the fundamentals of silicon, package, and board level interconnect technologies. The candidate is expected to have strong communications, project focus and execution skills. All Qualcomm employees are expected to actively support diversity in their teams, and in the Company.

Requirements

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ years of System/Package Design/Technology Engineering or related work experience.
• Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 3+ years of System/Package Design/Technology Engineering or related work experience.
• PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 2+ year of System/Package Design/Technology Engineering or related work experience.
• Understanding of the fundamentals of silicon, package, and board level interconnect technologies.
• Strong communications, project focus and execution skills.

Nice To Haves

• Ph. D degree in Mechanical engineering, Material science, Electrical/Microelectronics, or related engineering field.
• 6+ years of combined experience in Finite Element modeling and Analysis for IC electronic package and interconnects.
• 3+ years of experience in ANSYS (APDL/Workbench).
• 4+ years of direct work experience in Semiconductor and IC microelectronic packaging industry.
• Experience with the fundamentals of IC electronic packaging structures, assembly processes, reliability testing and analysis, CPI, Package-Board interaction, and design of experiments (DOE).
• Solid understanding of IC packaging materials and their thermo-mechanical behaviors.
• Hands-on FEA experience developing and improving BKMs for predictive modeling to guide package mechanical design and support manufacturing and reliability needs.
• Experience with material characterization/testing and developing new test methods to improve package FEA model accuracy and prediction correlation.
• Research and publications in FEA predictive modeling, Warpage, CPI, and Solder lifetime prediction
• Experience using internal AI tools to accelerate APDL coding and improve simulation workflows
• Strong analytical skills and a proven track record of project execution; excellent communication and presentation skills.
• Self-starter with high motivation and a strong commitment to product success; able to work flexible hours to support collaboration across APAC and the U.S.; occasional domestic and international travel may be required.

Responsibilities

• Development of mechanical FEA models (preferably using ANSYS APDL and Workbench)
• Maintain APDL macros/workflows
• Establish FEA methodologies/BKM for test correlation
• Material characterization
• Performing stress/mechanical analysis for IC package designs and failure prediction
• Warpage/Stress analysis
• Solder joint reliability (SJR) prediction
• Package assembly process simulation
• Chip package interaction (CPI) analysis
• Utilizing advanced Finite Element Analysis (FEA) techniques (sub-modeling approach, contact analysis, non-linear analysis)
• Utilizing test procedures for material characterization/testing

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior