Senior IC Packaging Development Engineer

NVIDIA•Santa Clara, CA

1d•$168,000 - $345,000

About The Position

We are looking for an experienced Engineer who will lead the development of rapid IC packaging of individual die, to enable Failure Analysis and NPI tasks ahead of high-volume manufacturing. This will include planning & driving related R&D with multiple internal and external partners and you will be responsible for establishing advanced packaging processes needed to meet our NPI goals regarding packaging turn-around-time, reliability, and chip-package interaction. Prior knowledge of Package related Failure Analysis is beneficial.

Requirements

B.S., M.S., or Ph.D., or equivalent experience in Materials Science, Mechanical Engineering, Electrical Engineering, Physics, or a related semiconductor field.
Deep understanding of flip-chip, 2.5D/3D packaging, wire bonding, and advanced substrate architectures.
12+ years of hands-on experience in IC packaging development and/or package design, NPI (New Product Introduction).
Familiarity with IC package EDA software (e.g., Cadence Allegro Package Designer) and Finite Element Modeling (FEM) tools like ANSYS or ABAQUS is a strong plus.
At a minimum, you’ll need basic understanding of advanced packaging related FA techniques and equipment, such as SEM, EDX, CSAM, X-Ray, and LIT.

Nice To Haves

Prior knowledge of Package related Failure Analysis is beneficial.

Responsibilities

Drive the process, mechanical, thermal, and material evaluation of the latest IC packages.
Manage rapid prototyping builds, package stack-ups, and assembly processes to bring new packaging architectures from concept to small volume for FA and NPI use cases.
Pioneer new packaging & die-level processing methodologies and evaluate innovative packaging materials (e.g., molding compounds, substrates, adhesives).
Coordinate comprehensive physical and electrical failure analysis on prototype builds, reliability-tested components to determine root causes of failures.
You’ll be embedded into the IC Failure Analysis team and collaborate with IC & Package design teams, process & product engineering.
Collaborate with foundries and OSAT (Outsourced Semiconductor Assembly and Test) partners to develop & test the required processes, tooling, and workflows.