Technology Development Foundry Engineering – Staff Engineer

Intel Corporation•Santa Clara, CA

11d•$133,800 - $255,200•Hybrid

About The Position

Join the Logic Technology Development (LTD) organization, a powerhouse of process technology innovation driving Intel's IDM 2.0 strategy and enabling the success of our global foundry customers. We are seeking a versatile Staff Engineer to be at the forefront of Intel's foundry transformation, serving as a pivotal technical partner who guides customers through the entire product development lifecycle. In this role, you will leverage multidisciplinary expertise spanning product/process integration, device engineering, and yield engineering to lead customers from pre-silicon evaluation and design tape-out through testing, validation, silicon qualification, and production ramp. This is a unique opportunity to apply broad technical leadership, solve complex challenges, face customers, and actively shape the future of the semiconductor industry in the AI era.

Requirements

Master's degree (with 3+ years of relevant industry experience) or PhD (with 1+ years of relevant industry experience) in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or a related engineering or physical science discipline.
1+ years of experience in at least one of the following areas: Product/Process Integration engineering, Device engineering, Yield engineering

Nice To Haves

Direct experience with Gate-All-Around (GAA) technology nodes.
Foundry customer engagement experience with a demonstrated customer-focused mindset.
Experience supporting or collaborating with fabless semiconductor companies during product development.
Strong communication, leadership, and stakeholder management skills.

Responsibilities

Drive end-to-end Multi-Project Wafer (MPW) and New Product Introduction (NPI) execution across the full manufacturing flow, from front-end processing through far backend operations, ensuring quality and on-time delivery.
Serve as the primary customer-facing interface for silicon execution including wafer status, silicon health, technical issues, process changes, and execution alignment.
Own identification and resolution of customer-specific integration challenges.
Drive enablement of customer-specific requirements through effective cross-functional coordination.
Serve as the primary customer interface for device performance, including manufacturing readiness reviews, performance roadmaps and projections, post-silicon characterization, model to hardware correlation, and resolution of customer-specific device issues.
Track device performance targets and process control capability while assessing alignment between silicon results and PDK expectations.
Drive device performance optimization through silicon learning, root-cause analysis, and cross-functional corrective actions to improve product readiness and close performance gaps.
Serve as the primary yield point of contact throughout the product lifecycle, from design tape-out through High Volume Manufacturing (HVM).
Develop predictive yield models to identify parametric and defect-related loss mechanisms and provide yield projections for test chips, shuttle vehicles, and production products.
Lead deep-dive investigations into yield signals and nonconformances, partnering with Process Integration, Device Engineering, and Defect Metrology teams to eliminate systematic yield losses. Perform root-cause analysis leveraging on state-of-the-art FI/FA.
Establish strong correlations between inline process metrics and end-of-line yield performance to improve process control and production predictability.