Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

Samsung Semiconductor•San Jose, CA

11d•Onsite

About The Position

Architecture Research Lab is focused on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. We explore new architectural ideas, evaluate their performance potential, and rapidly turn promising concepts into working designs that can be validated on real silicon. Our research is driven by emerging opportunities in data center and agentic AI workloads, where we investigate how CPU architecture can evolve to meet new performance and efficiency requirements. We also explore CPU-memory co-design from the CPU perspective, in alignment with the broader shift toward memory-centric architectures. A distinctive aspect of our team is the way we approach architecture research. We develop and apply AI-driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation. Rather than simply following established design flows, we continuously seek new ways to explore, evaluate, and realize CPU architectures. The role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed.

Requirements

Master’s degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or PhD with 5+ years of relevant experience
4+ years of experience in CPU microarchitecture or performance engineering
Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector unit
Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems
Hands-on experience with architectural simulators such as gem5
Proficiency in C/C++ and Python
Experience analyzing large-scale performance data and traces

Nice To Haves

Experience with AI-driven or agentic design workflows, including high-level design languages and AI-assisted RTL generation, or a strong interest in and ability to quickly learn such methods
Understanding of agentic AI workload execution patterns
Domain-specific experience in one or more of the following areas: Front-end: Branch prediction and decoupled fetch, particularly for compiler- or interpreter-driven workloads
Mid-end: RVV/SIMD, matrix/tensor engine design, and out-of-order vector execution
Back-end: LSU/MSHR design and prefetcher design for irregular access patterns
Experience with PPA trade-off analysis
Experience leading and mentoring junior engineers
Experience with CPU tapeout or silicon validation
Experience with patents or technical publications

Responsibilities

Propose new architecture ideas and take ownership of one or more microarchitectural domains, including front-end, mid-end, and back-end
Use AI-driven design methodologies to rapidly implement architectural ideas and validate them on real silicon
Build, extend, and validate performance models and architectural simulators
Perform CPI/IPC analysis and identify root causes of performance bottlenecks
Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models
Characterize workloads and benchmarks, including SPEC, server, client, AI/ML, agentic AI, and internal traces
Translate performance analysis and modeling results into architectural direction and design decisions
Drive research leading to patents and technical publications