Principal Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

Samsung Semiconductor•San Jose, CA

11d•$219,000 - $351,000•Onsite

About The Position

The Architecture Research Lab is focused on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. We explore new architectural ideas, evaluate their performance potential, and rapidly turn promising concepts into working designs that can be validated on real silicon. Our research is driven by emerging opportunities in data center and agentic AI workloads, where we investigate how CPU architecture can evolve to meet new performance and efficiency requirements. We also explore CPU-memory co-design from the CPU perspective, in alignment with the broader shift toward memory-centric architectures. A distinctive aspect of our team is the way we approach architecture research. We develop and apply AI-driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation. Rather than simply following established design flows, we continuously seek new ways to explore, evaluate, and realize CPU architectures. The role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed. As a Principal CPU Architecture & Performance Engineer, you will define the architectural vision and performance direction for next-generation CPU platforms. You will identify opportunities across emerging workloads, shape long-term architectural strategies, develop and refine performance models, and drive new microarchitectural concepts across multiple architectural domains. You will work closely with RTL design teams and cross-functional engineering partners to translate architectural vision into implementable designs, influence key technical decisions, and validate architectural choices from modeling through silicon. The role carries broad technical ownership, with the opportunity to establish new research directions, drive architecture across multiple generations of CPUs, and shape the fundamental design choices that determine future CPU performance and capabilities.

Requirements

Master’s degree in Computer Engineering, Computer Science, or a related field with 18+ years of relevant experience, or PhD with 15+ years of relevant experience
8+ years of experience in CPU microarchitecture, architecture research, or performance engineering, with a demonstrated track record of driving architectural direction
Extensive experience designing and evaluating high-performance CPU architectures, including RISC-V, ARM, or x86 cores; experience with GPU/NPU vector or accelerator architectures is also relevant
Proven ability to use quantitative performance analysis and modeling to identify architectural opportunities, evaluate system-level trade-offs, and influence major microarchitectural decisions
Deep expertise in at least one major microarchitectural domain, with the ability to drive architectural direction and technical decisions in that area: Front-end: Branch prediction, fetch/decode, instruction delivery, and decoupled front-end architectures; Mid-end: Out-of-order execution, scheduling, RVV/SIMD, vector execution, or matrix/tensor acceleration; Back-end: Load/store units, MSHRs, cache and memory systems, prefetching, or irregular memory access optimization
Hands-on experience building, extending, and applying architectural simulators and performance models, such as gem5, to guide architecture decisions
Strong programming skills in C/C++ and Python, with experience developing tools and automation for performance analysis and architectural exploration
Demonstrated ability to take architectural concepts from research and modeling through RTL implementation and silicon validation

Nice To Haves

Experience defining or influencing CPU architecture for emerging workloads, particularly AI/ML, agentic AI, or data center applications
Experience with AI-driven architecture and design methodologies, including AI-assisted architecture exploration, high-level design, or RTL generation
Strong perspective on memory-centric architectures and CPU-memory co-design, with experience translating memory-system characteristics into CPU architectural opportunities
Experience driving system-level PPA trade-offs across performance, power, area, and implementation complexity
Experience taking architectural concepts through RTL implementation, tape-out, and silicon validation
Experience leading cross-functional architecture initiatives and influencing technical direction across multiple engineering teams
Proven ability to mentor and develop senior technical engineers and shape architecture research across multiple domains
Track record of impactful architectural innovation through patents, publications, or deployed products

Responsibilities

Define the application-specialization direction for next-generation CPU cores, including agentic AI and memory-centric architectures, and lead the overall microarchitectural vision
Lead end-to-end performance analysis using architectural simulators and RTL, guiding key architectural trade-offs and decisions
Translate workload characterization and performance insights into architectural requirements and long-term design direction
Drive architecture-to-implementation alignment with design teams, ensuring architectural intent is carried through RTL and silicon
Mentor Senior and Staff engineers and provide technical leadership across multiple projects and architectural domains
Drive research and technical contributions leading to patents and publications