Senior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

Samsung Semiconductor•San Jose, CA

11d•Onsite

About The Position

Architecture Research Lab is focused on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. We explore new architectural ideas, evaluate their performance potential, and rapidly turn promising concepts into working designs that can be validated on real silicon. Our research is driven by emerging opportunities in data center and agentic AI workloads, where we investigate how CPU architecture can evolve to meet new performance and efficiency requirements. We also explore CPU-memory co-design from the CPU perspective, in alignment with the broader shift toward memory-centric architectures. A distinctive aspect of our team is the way we approach architecture research. We develop and apply AI-driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation. Rather than simply following established design flows, we continuously seek new ways to explore, evaluate, and realize CPU architectures. The role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed.

Requirements

Master’s with Computer Architecture, Computer Engineering, or a related field and 3+ years of experience or PhD degree in Computer Architecture, Computer Engineering, or a related field.
1+ years of experience in CPU microarchitecture or performance engineering.
Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems.
Hands-on experience with architectural simulators such as gem5.
Proficiency in C/C++ and Python.

Nice To Haves

Experience with RISC-V, ARM, or x86 CPU cores, or with GPU/NPU vector unit design.
Experience with or interest in AI-driven or agentic design workflows.
Understanding of execution patterns and characteristics of agentic AI workloads.
Domain-specific experience in the front-end, mid-end, or back-end areas described above.
Experience with PPA trade-off analysis.
Experience with CPU tape-out or silicon validation.
Experience with patents or technical publications related to CPU.

Responsibilities

Drive both microarchitectural research and performance modeling for next-generation CPU architectures.
Analyze emerging workloads, develop and refine performance models, identify architectural opportunities, and turn quantitative insights into new microarchitectural concepts.
Work closely with RTL design teams to evaluate, refine, and implement promising ideas, taking them from architectural modeling through RTL and silicon validation.
Collaborate with Staff and Principal Engineers, owning a specific microarchitectural domain from idea proposal through implementation and validation.
Participate in design implementation and validation using AI-driven design methodologies.
Run architectural simulations and performance models, and analyze results such as IPC, CPI stacks, latency, and throughput.
Identify performance bottlenecks and optimization opportunities across the front-end, mid-end, and back-end.
Characterize workloads and benchmarks to understand performance behavior and architectural opportunities.
Develop scripts and tools to automate and accelerate performance analysis and architectural exploration.
Contribute to patents and technical publications based on novel architectural research.