Senior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

Samsung Semiconductor•San Jose, CA

11d•$138,000 - $206,000•Onsite

About The Position

The Architecture Research Lab focuses on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. This involves exploring new architectural ideas, evaluating their performance potential, and developing working designs for validation on real silicon. The research is driven by opportunities in data center and agentic AI workloads, investigating how CPU architecture can evolve to meet new performance and efficiency requirements. The team also explores CPU-memory co-design from the CPU perspective, aligning with the shift toward memory-centric architectures. A distinctive aspect of the team is its use of AI-driven methodologies to accelerate architectural exploration, broaden the design space, and iterate quickly from ideas to implementation and silicon validation. The role offers an opportunity to work across the full spectrum of architecture research, including workload and performance analysis, microarchitectural innovation, architectural modeling, implementation, and silicon validation, while also shaping new methodologies for future CPU design. The role involves driving microarchitectural research and performance modeling for next-generation CPU architectures, analyzing emerging workloads, developing and refining performance models, identifying architectural opportunities, and translating quantitative insights into new microarchitectural concepts. Close collaboration with RTL design teams is expected for evaluating, refining, and implementing promising ideas, taking them from architectural modeling through RTL and silicon validation. The role offers significant ownership in shaping new CPU architectures and determining which ideas can deliver meaningful performance gains in real hardware.

Requirements

Master’s with Computer Architecture, Computer Engineering, or a related field and 3+ years of experience or PhD degree in Computer Architecture, Computer Engineering, or a related field
1+ years of experience in CPU microarchitecture or performance engineering
Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems
Hands-on experience with architectural simulators such as gem5
Proficiency in C/C++ and Python

Nice To Haves

Experience with RISC-V, ARM, or x86 CPU cores, or with GPU/NPU vector unit design
Experience with or interest in AI-driven or agentic design workflows
Understanding of execution patterns and characteristics of agentic AI workloads
Domain-specific experience in the front-end, mid-end, or back-end areas described above
Experience with PPA trade-off analysis
Experience with CPU tape-out or silicon validation
Experience with patents or technical publications related to CPU

Responsibilities

Collaborate with Staff and Principal Engineers, owning a specific microarchitectural domain from idea proposal through implementation and validation
Participate in design implementation and validation using AI-driven design methodologies
Run architectural simulations and performance models, and analyze results such as IPC, CPI stacks, latency, and throughput
Identify performance bottlenecks and optimization opportunities across the front-end, mid-end, and back-end
Characterize workloads and benchmarks to understand performance behavior and architectural opportunities
Develop scripts and tools to automate and accelerate performance analysis and architectural exploration
Contribute to patents and technical publications based on novel architectural research