Staff Digital Design Engineer

Renesas Electronics•Chandler, AZ

4d•Onsite

About The Position

Renesas Electronics is seeking a highly skilled and motivated Staff Digital Design Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications.

Requirements

>10 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management.
Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design.
Strong understanding of ASIC design methodology.
Strong understanding of Lint, CDC & RDC tools.
Strong understanding of block-level & chip-level verification techniques.
Strong & proven ability to debug both RTL & gate-level simulations.
Mandatory competence in written and verbal English.
Willingness to travel domestically or internationally on short notice.
Ability to work independently and collaboratively.

Nice To Haves

experience with Digital Signal Processing (DSP) concepts and hardware realizations.
experience with methodology and flow automation using appropriate scripting.
experience with mixed-signal design methodologies.
experience developing design constraints and hand-off to P&R.
experience with STA and timing closure.
experience with low-power design techniques, including clock and power gating (UPF).
experience with power analysis and optimization.
experience with advanced verification methodologies (UVM).
experience with industry-standard protocols such as AMBA or I2C.

Responsibilities

Ensuring digital development process is state-of-the-art and achieves budget, schedule, and project deliverable goals.
Designing digital RTL that meets timing, area, power and any adhering standards specifications.
Integrating design at the top level and running block & top-level simulations.
Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF.
Working closely with P&R team to generate a layout that meets timing, area, and power requirements.
Support DFT strategy and implementation, and review test case development.
Assisting with top level test-bench debug, and running RTL & gate level simulations
Working with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification.
Supporting analog team to develop AMS, System Verilog or Verilog-real behavioral models.
Developing detailed block & chip level design documents and collateral.
Holding and participating in key design reviews and completion of various checklists.
Perform silicon evaluation as required.
Document device errata, develop work-around solutions, implement engineering changes when necessary.