Digital Design Engineer

Qualcomm • San Diego, CA

1d • $121,800 - $182,600

About The Position

Qualcomm Technologies, Inc.’s high-speed parallel interfaces team is seeking an ASIC front-end design engineer to help architect, design, and implement DDR and die-to-die interfaces for high-speed compute and server systems. The role involves designing and developing RTL and implementing digital IP that connects SoCs to DRAM devices and provides reliable high-speed links in multi-die systems.

The engineer will work closely with systems architecture, verification, timing, and physical design teams to design and implement control and data-path blocks for SoC interfaces. The role requires digital IP design expertise using SystemVerilog, logic synthesis, linting, clock-domain-crossing analysis and best practices, low-power implementation and sign-off, and gate-level simulation debug. The position also involves cross-functional collaboration throughout implementation and silicon bring-up. Experience with high-speed parallel physical interfaces and low-power designs is a plus.

Requirements

• Bachelor’s degree in Science, Engineering, or a related field.
• Minimum 4 years of ASIC design, verification, or related work experience.
• Experience with digital IP design using SystemVerilog.
• Expertise in logic synthesis and linting checks.
• Knowledge of clock-domain-crossing best practices and analysis.
• Experience with low-power implementation and sign-off.
• Experience with design-for-test flows for stuck-at and TDF modes.
• Experience with gate-level simulation bring-up and debug.
• Ability to work closely with cross-functional teams in a fast-paced, dynamic environment.

Nice To Haves

• Prior experience with high-speed parallel physical-interface designs.
• Prior experience with low-power designs.
• Experience with high-speed, low-power digital logic design, ASIC front-end implementation tool flows, and silicon bring-up.
• BS with 4 years or MS with 2 years of relevant work experience.

Responsibilities

• Design and develop RTL for digital IPs supporting SoC-to-DRAM connections and high-speed links in multi-die systems.
• Design and implement control and data-path blocks for SoC interfaces.
• Work with systems architecture, verification, timing, and physical design engineers across implementation phases.
• Apply ASIC front-end implementation methodologies and support silicon bring-up.
• Perform digital IP design using SystemVerilog, logic synthesis, linting checks, clock-domain-crossing analysis, low-power implementation and sign-off, and gate-level simulation debug.
• Collaborate with cross-functional teams to enable implementation and silicon bring-up.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants, except for employees on sales-incentive plans.
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level