Digital Design Engineer

Credo•San Jose, CA

10h•$80,000 - $133,000

About The Position

As a Digital Design Engineer at Credo, you will perform front-end ASIC design, including designing and verifying complex logic blocks. You will collaborate with Physical Design and Integration teams to deliver successful tape-outs. The role includes writing microarchitecture and design specifications; architecting, implementing, and debugging logic blocks; integrating internal and external IP; supporting front-end integration activities; developing functional tests and testbenches; running RTL and gate-level verification and simulations; and working across engineering and product teams to bring up, validate, and debug chip features. The position offers a base salary range of $80,000–$133,000 per year. The base salary offer depends on factors including education, experience, training, skills, qualifications, and location. The position is also eligible for a discretionary bonus, equity, and medical and other benefits. Credo develops high-speed copper and optical interconnect products focused on fast, reliable, and energy-efficient system solutions. Its portfolio includes Active Electrical Cables, optical transceivers, memory solutions, and retimers and DSPs for optical and copper Ethernet and PCIe.

Requirements

Bachelor’s degree with two to seven years of experience, or Master’s degree with up to five years of experience, in Electrical/Electronic Engineering or Computer Engineering.
Understanding of digital logic design and knowledge of handling complex synchronous and asynchronous interfaces.
Knowledge of Verilog/SystemVerilog RTL design through relevant experience or coursework projects.
Knowledge of Verilog verification through relevant experience or coursework projects.
Knowledge of synthesis and static timing analysis.
Knowledge of scripting languages such as Python, Tcl, Perl, and shell.

Nice To Haves

Knowledge of UVM.
Knowledge of the IEEE 802.3 Ethernet physical layer.

Responsibilities

Write microarchitecture and/or design specifications.
Architect, design, implement, and debug complex logic blocks.
Understand and integrate complex IPs from internal and external IP vendors.
Support front-end integration activities such as Lint, CDC, synthesis, and ECO.
Develop functional tests and testbenches.
Run functional RTL and gate-level verification and simulations.
Work with ASIC design and verification, DFT, and physical design engineers to achieve a successful tape-out.
Collaborate with Software, Firmware, Applications, and Systems teams to ensure a high-quality product.
Bring up, validate, and debug functional features in the chip.