STA Signoff Flow, Principal AE

Cadence Systems•San Jose, CA

About The Position

At Cadence, employees are hired and developed as leaders and innovators who aim to make an impact on technology. In this senior role, the Principal AE performs static timing, glitch, and noise analysis using the Tempus Signoff tool and executes timing-analysis flows, ECO flows, CAD tools, and methodologies. The role works on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, and distributed and concurrent STA flows. The position works efficiently with R&D and customers to enable timing-analysis and ECO flows, including for newer advanced technologies. It performs timing correlation, tool-feature benchmarking, constraint validation, and spice analysis across technology nodes and customer designs. It also develops in-design timing ECO optimization solutions, with basic knowledge of place and route, clock tree, RC extraction, and UPF/CPF concepts. The Principal AE leads Tempus timing signoff campaigns at existing and new customers, automates flows using Perl, Tcl, and Python, and delivers technical training and seminars within Cadence and at customer sites. The role requires at least eight years of static timing analysis experience and the ability to lead and execute technical campaigns, perform timing and correlation benchmarks with Tempus, deliver reliable timing-analysis and ECO flows, collaborate with Cadence R&D on tool features and bug fixes, and work across physical-design areas such as timing analysis, place and route, extraction, and spice.

Requirements

At least 8 years of experience in static timing analysis.
Ability to lead and execute technical campaigns at internal and external customers.
Experience performing timing and correlation benchmarks with Cadence Tempus Signoff.
Ability to execute and deliver timing-analysis and ECO flows while ensuring solution integrity.
Ability to work effectively with Cadence R&D to enable tool features and resolve tool bugs.
Knowledge across physical-design areas, including timing analysis, place and route, extraction, and spice.
Basic knowledge of place and route, clock tree, RC extraction, and UPF/CPF concepts.
Experience or ability to automate flows using Perl, Tcl, and Python.

Responsibilities

Perform static timing, glitch, and noise analysis using the Tempus Signoff tool.
Execute and deliver timing-analysis flows, ECO flows, CAD tools, and methodologies.
Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, and distributed and concurrent STA flows.
Work with R&D and customers to enable timing-analysis and ECO flows, including for advanced technologies.
Perform timing correlation, tool-feature benchmarking, constraint validation, and spice analysis across technology nodes and customer designs.
Work on in-design timing ECO optimization solutions.
Lead Tempus timing signoff campaigns at existing and new customers.
Automate flows using Perl, Tcl, and Python.
Deliver technical training and seminars within Cadence and at customer sites.
Lead and execute technical campaigns at internal and external customers.
Execute timing and correlation benchmarks using Cadence Tempus Signoff.
Ensure the integrity of delivered timing-analysis and ECO solutions.
Work with Cadence R&D to enable tool features and close tool bug fixes.
Work across physical-design areas, including timing analysis, place and route, extraction, and spice.