Application Engineer Architect (STA SignOff)

Cadence Design Systems•San Jose, CA

2d•$154,000 - $286,000•Onsite

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
BS/MS in Electrical Engineering, Computer Engineering, or related field.
Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems.
Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
Proven track record of leading technical teams and driving customer success at executive levels.
Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.

Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable.

Lead technical engagements with customers and partners to drive & adoption of Cadence signoff portfolio.
Work closely with design teams to meet customer success metrics, guide adoption of Cadence’s timing signoff & closure and AgenticAI features across advanced nodes (5nm and below).
Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing sigoff & closure, STA, IR Drop, and power/timing closure.
Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.