SRAM Design Lead

Micron•Boise, ID

1d•$153,000 - $267,000

About The Position

Micron Technology is seeking an experienced SRAM Design Engineer to develop high-performance, low-power embedded memory IP and testchip content for advanced semiconductor technologies. The role spans the full memory-development lifecycle, from architecture definition and transistor-level circuit design through schematic development, layout support, SPICE verification, timing and power characterization, compiler enablement, and pre- and post-silicon validation. The position requires hands-on expertise in SRAM and register-file design, memory arrays and bitcells, read/write datapaths, sense amplifiers, address decoding, control logic, assist techniques, and PPA tradeoffs. The engineer will collaborate with layout, CAD, manufacturing-process, testchip, product, silicon-test, and foundry teams to develop reliable, production-ready memory solutions and correlate models with measured silicon behavior. Responsibilities also include supporting configurable memory compilers, automating design and characterization flows, planning testchips, mentoring engineers, and exploring AI-assisted engineering workflows with human technical review.

Requirements

BS, MS, or PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field.
Proven experience in SRAM, register-file, ROM, DRAM peripheral, or other custom-memory circuit design.
Strong knowledge of CMOS transistor-level circuit design, memory architecture, static and dynamic timing behavior, power analysis, signal integrity, and process variation.
Hands-on experience with Cadence Virtuoso and SPICE-class simulators such as HSPICE, Spectre, or FineSim.
Experience performing PVT-corner, Monte Carlo, parasitic-aware post-layout, and power/timing characterization analyses.
Ability to translate product or testchip requirements into circuit architecture, measurable design targets, verification plans, and release criteria.
Experience collaborating with layout, CAD, process/foundry, verification, product, and chip-testing groups.
Clear technical communication and interpersonal skills.
Ability to operate in a structured manner and solve problems.
Ability to debug complex circuit or silicon issues using data and waveform evidence.

Nice To Haves

Experience developing low-power SRAM or register-file compilers across multiple technology nodes and foundries.
Experience with bitcell stability analysis, assist schemes, retention modes, redundancy, test modes, compiler architecture, and generated-memory validation.
Track record of taking memory IP from product definition and circuit design through layout, characterization, release, silicon correlation, and customer integration.
Experience planning memory testchips and partnering with silicon-test teams on characterization, debug, and correlation.
Proficiency in Python, along with Tcl, Perl, SKILL, or related programming languages, for simulation, characterization, regression, and design-flow automation.
Familiarity with RTL-to-GDS or digital-on-top methodologies for memory periphery and control logic, alongside full-custom array and critical-circuit design.
Experience applying agentic AI, coding assistants, or custom LLM agents to specification processing, design automation, validation, or engineering productivity.

Responsibilities

Design and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.
Develop and verify memory-array subsystems, including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.
Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
Own transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation, and waveform/debug reviews.
Drive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.
Define timing, power, noise, and functional characterization methodologies and generate validated data for memory models, compiler views, SoC integration, and product signoff.
Partner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock and control distribution, parasitic reduction, and layout-dependent effects.
Support memory-compiler development by defining legal configurations, architecture templates, circuit collateral, generation rules, validation checks, and release-quality views for multiple macro instances.
Develop or improve automation for macro assembly, simulation setup, corner execution, results extraction, characterization, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages.
Plan and support SRAM testchips, including memory-instance selection, PPA objectives, test access, measurement structures, characterization plans, and alignment with process-learning goals.
Lead pre-silicon verification, silicon bring-up, post-silicon characterization, failure debug, and model-to-silicon correlation in partnership with product and silicon-test teams.
Create circuit specifications, design-review material, verification plans, characterization reports, and release documentation with traceable assumptions and decisions.
Mentor engineers on memory-circuit fundamentals, simulation, PPA analysis, debug methods, and reusable build practices.
Explore AI-assisted engineering workflows for specification extraction, circuit and block partitioning, test-mode enrichment, design-flow automation, regression analysis, and documentation while maintaining human technical review.