The SRAM Lab is seeking an intern to support the development, simulation, and optimization of SRAM circuits for next-generation semiconductor products. The lab integrates circuit analysis and layout strategies to deliver memory solutions that meet power, performance, and area requirements for AI and mobile ecosystems. The intern will contribute to projects spanning architecture, schematic design, and silicon-level verification, and research architectures that improve computing-platform efficiency and SoC compatibility. The role requires daily onsite presence at Samsung Semiconductor’s San Jose headquarters and reports to the Sr. Director, SRAM Design. The internship includes learning about SRAM compilers, bit-cells, write/read operations, SRAM design procedures, schematic composition, and simulation debugging. The intern will use industry-standard EDA tools and document design processes, simulation results, and findings in technical reports or presentations.
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Career Level
Intern