The SRAM Lab is seeking an intern to support the development, simulation, and optimization of SRAM circuits. The lab designs, develops, and optimizes advanced SRAM circuits for next-generation semiconductor products, combining circuit analysis and layout strategies to meet power, performance, and area requirements for AI and mobile applications. The intern will contribute to SRAM projects spanning architecture, schematic design, and silicon-level verification, and will research architectures to improve computing-platform efficiency and SoC compatibility. The role is based onsite daily at the San Jose headquarters and reports to the Sr. Director, SRAM Design. The internship offers exposure to SRAM compilers, bit-cells, read/write operations, SRAM design procedures, schematic composition, simulation, and debugging.
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Career Level
Intern