Sr. Staff Physical Design Engineer

Advanced Micro Devices, Inc•Austin, TX

About The Position

Join AMD’s experienced physical design team working on graphics IP for next-generation AI data center chips. The role owns and drives complex physical design work for multi-million-gate blocks, delivering against challenging performance, power, and area targets using advanced process technologies. The engineer partners closely with RTL design and other engineering teams throughout the project lifecycle, from floorplanning, synthesis, and placement through clock tree synthesis, routing, timing closure, extraction, physical verification, and final signoff. The position also offers opportunities to lead technical execution, establish design methodologies, improve automated design flows, and mentor other engineers. The ideal candidate is a collaborative technical leader with strong analytical thinking, clear communication, and attention to detail. They take ownership of execution, communicate issues and priorities across geographically distributed teams, provide technical guidance and mentorship, and balance multiple priorities to support successful project delivery. The role is based in Austin, Texas, or Santa Clara, California, and is not eligible for visa sponsorship. AMD may use artificial intelligence to help screen, assess, or select applicants. This posting is for an existing vacancy.

Requirements

Strong experience in physical design for high-performance semiconductor designs, including timing closure and physical signoff.
Experience with synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control-logic applications.
Experience with floorplanning, clock tree synthesis, clock and power gating, scan stitching, routing, extraction, and physical verification.
Experience establishing design methodologies, integrating IP, performing logic-equivalence checks, and validating physical, timing, and electrical quality for large IP delivery.
Experience with advanced process technologies, including N2P or below.
Proficiency with Python and TCL for design-flow development and automation.
Experience leading engineers through design closure and providing technical mentorship.
Familiarity with RTL design, logic-level optimization, and computer organization/architecture.

Nice To Haves

Experience with physical design and signoff tools such as Synopsys ICC2, ICC, Fusion Compiler, PrimeTime and StarRC; Mentor Graphics Calibre; Apache RedHawk; and Cadence Innovus and Genus.
Experience applying or developing AI techniques for performance, power, and area optimization is desirable.
Bachelor’s or Master’s degree in Electronics/Electrical Engineering preferred.

Responsibilities

Own the physical design of complex, multi-million-gate graphics IP blocks and drive designs toward required performance, power, and area targets.
Partner with RTL design teams to identify frequency bottlenecks and address logic-level and timing issues early in the project lifecycle.
Drive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.
Perform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff.
Establish and improve physical design methodologies for large IP delivery, including IP integration and design-quality checks.
Drive design optimization for timing, power, area, and design-cycle efficiency.
Develop and enhance scripts and automated design flows to improve physical design execution.
Provide technical leadership and mentoring to engineers throughout design closure.
Collaborate across geographically distributed engineering teams to deliver projects against technical requirements.