Sr. Staff Design Engineer

Lattice Semiconductor•San Jose, CA

About The Position

Lattice is seeking a Sr. Staff Design Engineer to perform RTL design and verification, applying knowledge of Lattice Semiconductor products and customer applications across market segments. The role develops complex systems from concept through board-level validation using Lattice FPGA architectures and tool flows; builds embedded systems in Lattice FPGAs, including microprocessor designs and embedded software; integrates IP into FPGA software flows; and supports end-to-end system implementation. It also involves analyzing hardware capabilities, shaping customer solutions, architecting soft IP with detailed specifications, and coordinating development with software and applications teams. The position focuses on DDR memory controller soft IP architecture and development, performance optimization, FPGA design and implementation, integration with third-party hardened PHYs, timing analysis and constraints, RISC-V system design, customer support, quality review, and test development. A bachelor's degree in Electronics Engineering, Applied Physics, or a related field and eight years of experience as a Design Engineer or in a related field are required, along with the specified FPGA, ASIC, interface, protocol, and validation experience. The role may be eligible for variable or incentive compensation and/or equity, and for a comprehensive benefits package that may include healthcare and retirement plans and paid time off. Pay varies by location and job-related qualifications. The position requires successful background and reference checks and proof of U.S. work authorization.

Requirements

Bachelor’s degree in Electronics Engineering, Applied Physics, or a related field.
Eight years of experience as a Design Engineer or in a related field.
Experience in FPGA and SoC ASIC development.
Experience developing IP for FPGA and ASIC products.
Experience in FPGA RTL design, logic verification, debugging, and timing closure.
Experience with DDR protocols such as DDR3, DDR4, LPDDR4, and DDR5.
Experience with high-speed interface subsystems.
Experience with high-speed protocols such as PCIe, Ethernet, and MIPI.
Experience with peripheral IPs such as UART, SPI, I2C, and I3C.
Experience in hardware validation and hardware interoperability testing.

Responsibilities

Perform RTL design and verification, applying expertise in Lattice products and customer applications.
Develop complex systems from concept through board-level validation using Lattice FPGA architectures and tool flows.
Build embedded systems within Lattice FPGAs, including microprocessor designs and embedded software.
Integrate IP into FPGA software flows and support end-to-end system implementation.
Analyze hardware capabilities and contribute to customer solution strategies.
Architect soft IPs, create detailed technical specifications, and coordinate development efforts.
Collaborate with software and applications teams to communicate requirements, resolve issues, and drive enhancements.
Architect and develop DDR memory controller soft IPs.
Optimize soft IPs for performance, including latency, size, and frequency.
Design and implement FPGA solutions using software primitives.
Integrate third-party hardened PHYs.
Provide team leadership and manage stakeholders.
Perform Static Timing Analysis (STA) and write constraints.
Design and evaluate RISC-V-based systems.
Support customers and resolve issues.
Review the quality of third-party deliverables.
Develop tests to validate implementations and ensure quality.