Sr. SOC Physical Verification Engineer (Silicon Engineering)

SpaceX•Palo Alto, CA

About The Position

SpaceX is seeking a motivated, proactive, and intellectually curious engineer to work with cross-disciplinary teams spanning systems, firmware, architecture, design, validation, product engineering, and ASIC implementation. The role develops next-generation silicon for deployment in space and ground infrastructure, supporting the performance and capabilities of the Starlink network. The engineer will own full-chip physical verification signoff, develop and optimize verification flows for advanced-node SoCs, interpret foundry design rules, debug violations, and coordinate tapeout readiness across design teams. The role also includes working directly with foundries and using AI agents to automate verification and reporting workflows.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science.
At least 5 years of industry experience in ASIC and/or physical design flow development.
Ability to work extended hours and weekends as needed to meet critical project milestones.
Must meet SpaceX ITAR eligibility requirements: be a U.S. citizen or national, U.S. lawful permanent resident, refugee, or asylee, or be eligible to obtain the required U.S. Department of State authorizations.

Nice To Haves

Experience and deep understanding of SoC top-level physical design flows, including floor-planning, I/O, bump and RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, and special interface/interconnect planning and implementation.
Experience in IP integration, such as memories, I/Os, analog IPs, SerDes, and DDR.
Deep expertise in DRC, LVS, PERC, and ESD verification methodologies.
Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus.
Direct foundry DRM experience, including reading, interpreting, and implementing complex rule decks.
Experience at advanced nodes (4 nm and below).
Experience with large SoC designs (over 10 million gates) with frequencies above 1 GHz.
Excellent scripting skills, including csh/bash, Perl, Python, TCL, and Makefile.
Self-driven approach, can-do attitude, and ability to work in a dynamic group environment.

Responsibilities

Own and execute full-chip DRC, LVS, ESD, PERC, and antenna signoff using tools such as Calibre, ICV, or Pegasus.
Develop, maintain, and optimize physical verification flows for advanced-node SoCs.
Interpret and implement foundry Design Rule Manuals, translating rule updates into verified flow changes.
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
Perform ESD verification, validating protection strategies, current paths, and CDM/HBM compliance.
Drive tapeout readiness by coordinating signoff across block, top-level, and hard IP design teams.
Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
Develop or modify design flows to meet design-quality and chip-integration requirements.
Leverage AI agents to automate rule-deck validation, violation triage, and signoff-reporting workflows.

Benefits

Potential long-term incentives, including company stock, stock options, or long-term cash awards.
Potential discretionary bonuses.
Ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
Comprehensive medical coverage.
Vision coverage.
Dental coverage.
401(k) retirement plan.
Short- and long-term disability insurance.
Life insurance.
Paid parental leave.
Various other discounts and perks.
May accrue 3 weeks of paid vacation.
Eligible for 10 or more paid holidays per year.
Exempt employees are eligible for 5 days of sick leave per year.