Sr Principal Application Engineer

Cadence Systems • San Jose, CA

1d

About The Position

At Cadence, the Sr Principal Application Engineer works hands-on with customers on backend digital design implementation and signoff, from RTL to GDSII. The role leads technical campaigns and strategies for digital implementation, drives improvements in power, performance, and area (PPA), and supports critical customer flagship product tape-outs. The engineer works closely with R&D to improve tools and methodologies, and modifies or extends design flows using Tcl and other programming skills to meet objectives and improve results.

Requirements

• Minimum MS degree in Computer Science/Engineering, Electrical Engineering, or a related field, plus 10+ years of industry experience.
• Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis.
• Experience with IC digital implementation flows and backend EDA tools, including synthesis, place and route, IR drop, backend design timing and power closure, and RTL to GDSII.
• Experience scripting in Perl, Tcl, or Python to automate work and implement process improvements.
• Experience with floor planning and power planning for low-power SoC designs.
• Experience with IC digital implementation flows and front-end EDA tools, including synthesis, DFT, and logical equivalence checking.
• Hands-on experience with floorplanning, place and route, timing analysis, and signoff.
• Strong customer-facing communication and problem-solving skills.
• Strong verbal, written, and customer communication skills.
• Strong personal drive for continuous learning and expanding professional skillsets.

Nice To Haves

• Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus.
• Experience with advanced clock tree synthesis techniques, including SoC clock distribution, clock mesh, and H-tree.
• Experience with multiple design closure areas, including timing, DRC, LVS, and EMIR.
• Experience with advanced technology nodes, including sub-5nm and below.
• Experience developing, debugging, and optimizing SoC design flows to achieve best PPA.
• Preferably, hands-on place-and-route, timing analysis, and signoff experience with the Cadence tools suite.

Responsibilities

• Work hands-on with Cadence customers on backend digital design implementation and signoff, including synthesis, place and route, design closure, and timing and power signoff from RTL to GDSII.
• Lead technical campaigns and strategies in RTL-to-GDSII digital implementation.
• Drive improvements in power, performance, and area (PPA).
• Deliver technical presentations and lead discussions internally and with customers.
• Work closely with R&D to enhance tools and methodologies to meet and exceed customer requirements with high quality.
• Support execution of critical customer flagship product tape-outs.
• Amend and augment flows using Tcl and/or other programming skills to meet objectives and improve results.

Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical plan options
• Dental plan options
• Vision plan options
• Incentive compensation may include bonus and equity

What This Job Offers

• Job Type: Full-time
• Career Level: Principal