Sr Principal Application Engineer

Cadence Design Systems•San Jose, CA

23h•$148,400 - $275,600

About The Position

Cadence is seeking a Senior Principal Application Engineer to work hands-on with customers on backend digital design implementation and signoff, including synthesis, place and route, design closure, timing and power signoff, and RTL-to-GDSII flows. The role leads technical campaigns and strategies for digital implementation, drives improvements in power, performance, and area (PPA), and supports critical customer flagship-product tape-outs. The engineer delivers technical presentations and leads discussions with customers and internal teams, while working closely with R&D to improve tools and methodologies. The role also involves amending and augmenting flows with Tcl or other programming skills to meet objectives and improve results.

Requirements

Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, plus 10 or more years of industry experience.
Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis.
Experience with IC digital implementation flows and backend EDA tools, including synthesis, place and route, IR drop, backend timing and power closure, and RTL-to-GDSII.
Experience scripting in Perl, Tcl, or Python to automate work and implement process improvements.
Experience with floorplanning and power planning for low-power SoC designs.
Experience with front-end EDA tools and flows, including synthesis, DFT, and logical equivalence checking.
Hands-on experience with floorplanning, place and route, timing analysis, and signoff.
Knowledge of advanced clock-tree synthesis techniques, including SoC clock distribution, clock mesh, and H-tree.
Strong customer-facing communication and problem-solving skills.
Strong verbal and written communication skills, including customer communication.
Personal drive for continuous learning and expanding professional skillsets.

Nice To Haves

Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus.
Experience with multiple design-closure activities, including timing, DRC, LVS, and EMIR.
Experience with advanced technology nodes below 5nm.
Good hands-on experience with Cadence tools for floorplanning, place and route, timing analysis, and signoff.

Responsibilities

Work hands-on with Cadence customers on backend digital design implementation and signoff, including synthesis, place and route, design closure, timing and power signoff, and RTL-to-GDSII.
Lead technical campaigns and strategies in RTL-to-GDSII digital implementation.
Drive improvements in power, performance, and area (PPA).
Deliver technical presentations and lead discussions internally and with customers.
Work with R&D to enhance tools and methodologies to meet or exceed customer requirements.
Support execution of critical customer flagship-product tape-outs.
Amend and augment flows using Tcl and/or other programming skills to meet objectives and improve results.