SPE Analog Engineering

Rambus•Morrisville, NC

3d•$169,400 - $254,000•Hybrid

About The Position

The candidate will join Rambus Memory Interface Chips BU’s design group, which specifies, architects, executes, and productizes leading-edge memory interface buffer chips for DDR5, DDR6, and beyond. The role owns analog and mixed-signal designs at chip and block level, with particular focus on high-speed data receivers. It involves architecting, designing, simulating, and characterizing high-performance, low-power high-speed circuits, as well as modeling designs at different levels of detail to support tradeoff analysis and voltage and timing budgets. The position also supervises analog layout for critical I/O blocks and works with cross-functional teams across geographies and time zones. Other work includes design documentation, supporting and debugging post-silicon validation, and correlating silicon results with simulation. Rambus uses a hybrid approach for most office-based roles, encouraging employees to work onsite an average of at least three days per week and remotely for two days. This is a full-time position with a U.S. salary range of $169,400 to $254,000. Starting pay depends on job-related skills, experience, qualifications, work location, and market conditions.

Requirements

MSEE or Ph.D.
10 or more years of analog or mixed-signal circuit design experience.
Understanding of signal-integrity and power-integrity principles and their interaction with receiver front-end principles.
Team-oriented, with good written and verbal communication skills.
Self-motivated, thorough, and detail-oriented, with the ability to work across multiple functional teams and follow good engineering practices.

Nice To Haves

Direct chip design experience in DDR interface design.
Experience with Verilog coding.

Responsibilities

Own analog and mixed-signal designs at chip and block level, especially high-speed data receivers.
Architect, design, simulate, and characterize high-performance, low-power, high-speed circuits, including receivers, samplers, and signal-conditioning circuits.
Model designs at chip and block level and at varying levels of detail for design tradeoff analysis and voltage and timing budgeting.
Supervise analog layout engineering, ensuring attention to detail for high-performance analog layout on critical I/O blocks.
Work with cross-functional teams across geographies and time zones to support engagement and execution.
Document designs.
Guide and debug post-silicon validation.
Correlate silicon results with simulation.