SoC Validation Engineer – Power Management

Intel•Folsom, CA

1d•Hybrid

About The Position

Intel is seeking a motivated and experienced SoC Validation Engineer to join its Power Management Validation team. The engineer will validate power management architectures and features for next-generation products, helping ensure design quality, functionality, and power efficiency. The role involves developing validation strategies, executing test plans, and driving debug activities across complex SoC designs. The engineer will work with architecture, design, and verification teams to validate features such as Dynamic Voltage and Frequency Scaling (DVFS), power gating, clock gating, reset flows, low-power states, thermal management, and telemetry. The role also contributes to advanced validation environments, identifies design issues early in development, and drives solutions that improve product quality and readiness. The position is within Intel's Data Center Group (DCG), which develops technologies for data center computing, storage, and networking.

Requirements

Bachelor's degree and 6+ years, master's degree and 4+ years, or PhD and 2+ years in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
10+ years of experience in pre-silicon validation, functional validation, design verification, or silicon validation.
Strong understanding of digital design fundamentals, computer architecture, and SoC design concepts.
Strong knowledge of SystemVerilog and UVM-based validation methodologies.
Experience with simulation or emulation environments and debugging and root-cause analysis skills.
Knowledge of Python, Perl, Shell, or similar scripting languages.

Nice To Haves

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience validating power management architecture and features in complex SoC designs, including DVFS, power gating, clock gating, low-power state management, reset and power sequencing, and thermal management.
Experience developing validation plans, test content, and coverage-driven validation strategies.
Experience in functional validation, design verification, coverage-driven verification, emulation-based validation, low-power verification methodologies, reset validation, power state validation, or telemetry feature validation.
Familiarity with assertion-based verification, formal verification, and advanced validation automation techniques.
Demonstrated ability to lead technical initiatives and mentor engineers.
Strong collaboration skills and ability to work effectively across architecture, design, and validation teams.
Experience leveraging AI and advanced analytics to improve validation productivity and quality.
Passion for innovation, continuous improvement, and technical excellence.
Excellent analytical, problem-solving, and communication skills.

Responsibilities

Develop and execute comprehensive validation plans to ensure power management features meet architectural and functional specifications.
Design, develop, and maintain validation environments, automated test content, and debug infrastructure for power management validation.
Validate DVFS, power gating, clock gating, low-power states and transitions, reset and power sequencing, thermal management features, and telemetry and monitoring logic.
Develop validation content and infrastructure using SystemVerilog, UVM, simulation, and emulation platforms.
Execute simulation and emulation workloads to validate design functionality and identify issues early in product development.
Analyze validation results, coverage metrics, and performance data to improve design quality and validation effectiveness.
Drive root cause analysis, debug, and resolution of complex design issues with architecture, RTL design, and verification teams.
Develop and maintain automation frameworks, regression environments, dashboards, and data analysis tools to improve validation efficiency and coverage.
Review architecture specifications and design changes to assess validation impact and ensure comprehensive feature coverage.
Contribute to validation methodology improvements and best practices across product generations.
Mentor junior engineers and provide technical leadership on complex validation and debug challenges.
Explore new technologies, automation techniques, and AI-assisted solutions to improve execution and outcomes.