SoC Validation Engineer – Power Management

Intel Corporation•Santa Clara, CA

2d•$164,470 - $269,100•Hybrid

About The Position

Intel is seeking an experienced SoC Validation Engineer to join its Power Management Validation team in the Data Center Group. The role validates power management architectures and features for next-generation products, helping ensure design quality, functionality, and power efficiency. The engineer will develop validation strategies and test plans, execute validation, and drive debug across complex SoC designs. The position works closely with architecture, design, and verification teams on features such as Dynamic Voltage and Frequency Scaling (DVFS), power gating, clock gating, reset flows, low-power states, thermal management, and telemetry. The engineer will contribute to validation environments, identify design issues early, and help improve product quality and readiness. The role also offers opportunities to provide technical leadership and mentor junior engineers. The role is based at an Intel site in the United States and is eligible for a hybrid work model, with time split between the assigned site and off-site. The posted annual target compensation range is $164,470 to $269,100, with pay depending on work location and job-related factors.

Requirements

A bachelor's degree and 6 or more years, a master's degree and 4 or more years, or a Ph.D. and 2 or more years in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
10 or more years of experience in pre-silicon validation, functional validation, design verification, or silicon validation.
Strong understanding of digital design fundamentals, computer architecture, and SoC design concepts.
Strong knowledge of SystemVerilog and UVM-based validation methodologies.
Experience with simulation or emulation environments, debugging, and root-cause analysis.
Knowledge of Python, Perl, Shell, or similar scripting languages.

Nice To Haves

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience validating power management architecture and features in complex SoC designs, including DVFS, power gating, clock gating, low-power state management, reset and power sequencing, or thermal management.
Experience developing validation plans, test content, and coverage-driven validation strategies.
Experience in functional validation, design verification, coverage-driven verification, emulation-based validation, low-power verification, reset validation, power-state validation, or telemetry feature validation.
Familiarity with assertion-based verification, formal verification, and advanced validation automation techniques.
Demonstrated ability to lead technical initiatives and mentor engineers.
Strong collaboration skills and ability to work effectively across architecture, design, and validation teams.
Experience leveraging AI and advanced analytics to improve validation productivity and quality.
Passion for innovation, continuous improvement, and technical excellence.
Excellent analytical, problem-solving, and communication skills.

Responsibilities

Develop and execute validation plans to ensure power management features meet architectural and functional specifications.
Design, develop, and maintain validation environments, automated test content, and debug infrastructure.
Validate DVFS, power and clock gating, low-power states and transitions, reset and power sequencing, thermal management, and telemetry and monitoring logic.
Develop validation content and infrastructure using SystemVerilog, UVM, simulation, and emulation platforms.
Execute simulation and emulation workloads to validate functionality and identify issues early in product development.
Analyze validation results, coverage metrics, and performance data to improve design quality and validation effectiveness.
Perform root-cause analysis, debug, and drive resolution of complex design issues with architecture, RTL design, and verification teams.
Develop and maintain automation frameworks, regression environments, dashboards, and data analysis tools.
Review architecture specifications and design changes to assess validation impact and ensure feature coverage.
Contribute to validation methodology improvements and best practices across product generations.
Mentor junior engineers and provide technical leadership on complex validation and debug challenges.
Explore new technologies, automation techniques, and AI-assisted solutions to improve execution and outcomes.