SoC Physical Design Engineer, PnR

Apple • San Jose, CA

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About The Position

Apple is hiring a SoC Physical Design Engineer for physical implementation of design partitions, from netlist to tapeout, for a highly complex SoC using innovative process technology. The role collaborates with architecture, CAD, timing, and logic design teams to help deliver high-quality designs. The engineer works across backend chip design and physical implementation, including physical synthesis, floor planning, place and route, power grid design, static timing analysis, physical design verification, and EMIR analysis.

Requirements

• Bachelor of Science degree; 0 or more years of experience.
• Basic understanding of logic gates.
• Strong teamwork skills and ability to collaborate with multiple functional teams across a variety of fields.
• Experience with one or more of Verilog, VHDL, Python, Perl, TCL, or SPICE.

Nice To Haves

• Previous internship or co-op, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.

Responsibilities

• Work with the logic design team to understand partition architecture and drive physical design considerations early in the design cycle.
• Complete netlist-to-GDS2 implementation for assigned partitions while meeting schedule and design goals.
• Perform timing, physical, and electrical verification, and drive signoff closure for partitions.
• Resolve and improve physical design and flow issues, identify potential solutions, and drive their execution.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level