SoC Physical Design Engineer, PnR

Apple • San Jose, CA

2d

About The Position

The SoC Physical Design Engineer is responsible for the physical implementation of design partitions, from netlist to tapeout, for a highly complex SoC using innovative process technology. The role collaborates with architecture, CAD, timing, and logic design teams and contributes to delivering high-quality designs. Work includes physical synthesis, floor-planning, place and route, power grid design, static timing analysis, physical design verification, and EMIR analysis.

Requirements

• Bachelor of Science degree.
• Basic understanding of logic gates.

Nice To Haves

• Previous internship or co-op experience, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
• Strong teamwork skills and ability to collaborate with multiple functional teams across different fields.
• Experience with Verilog, VHDL, Python, Perl, TCL, and/or SPICE.

Responsibilities

• Work with the logic design team to understand partition architecture and drive physical design considerations early in the design cycle.
• Complete netlist-to-GDS2 implementation for design partitions while meeting schedule and design goals.
• Perform timing, physical, and electrical verification and drive signoff closure for partitions.
• Resolve and improve physical design and flow issues, identify potential solutions, and drive their execution.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level