SoC Management Subsystem Architect

Majestic Labs • Los Altos, CA

9h

About The Position

Majestic Labs is seeking a seasoned SoC Architect to lead the design and integration of the management subsystem within its AI acceleration platform. The role defines and drives SoC-level architecture for control and management flows, integrating ARM cores, interconnects, high-speed I/O, and system management interfaces. It involves close collaboration with peer architects and hardware, firmware, and system engineers to create a cohesive design connecting silicon and software. This is a hands-on architecture position combining technical depth, system-level thinking, and cross-domain leadership in a fast-moving startup environment.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 6 years of experience in SoC architecture and design, with an emphasis on management or control subsystems.
• Proven experience with ARM core integration, PCIe, DDR/LPDDR, and peripheral interfaces such as SPI, I2C, and UART.
• Strong understanding of SoC design flows, memory hierarchy, and interconnect fabrics.
• Hands-on experience in control path design, driver interfaces, and interrupt management.
• Solid communication and teamwork skills, with the ability to lead cross-functional architectural discussions.

Nice To Haves

• Experience with AI/ML acceleration hardware or high-performance compute SoCs.
• Knowledge of board-level integration and hardware-software co-validation.
• Familiarity with silicon prototyping, emulation, or FPGA-based validation.
• Expertise in low-power design and high-bandwidth interconnect architectures.
• Deep experience with debug tools such as CoreSight, trace analyzers, and profilers, and with performance instrumentation.

Responsibilities

• Define and own the management subsystem architecture for Majestic’s AI SoC.
• Integrate ARM cores (CSS / Cortex-A) and associated subsystems for control, configuration, and monitoring.
• Architect PCIe connectivity and high-bandwidth I/O for robust host and device communication.
• Specify and integrate DDR/LPDDR interfaces and memory management structures.
• Design peripheral and control interfaces, including SPI, I2C, UART, GPIO, and system control buses.
• Develop scheduler and interrupt schemes, driver-facing control paths, and configuration frameworks.
• Integrate and optimize debug and trace infrastructures, including CoreSight, profilers, and diagnostic tools.
• Collaborate with RTL, verification, firmware, and board teams on hardware-software co-design.
• Drive tradeoffs and decisions to achieve performance, power, and area targets across the SoC.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior