SOC Engineering, Architect- 19169

Synopsys•Sunnyvale, CA

4d•$209,000 - $313,000•Onsite

About The Position

SYNOPSYS IS THE LEADER IN ENGINEERING SOLUTIONS FROM SILICON TO SYSTEMS, ENABLING CUSTOMERS TO RAPIDLY INNOVATE AI-POWERED PRODUCTS. WE DELIVER INDUSTRY-LEADING SILICON DESIGN, IP, SIMULATION AND ANALYSIS SOLUTIONS, AND DESIGN SERVICES. WE PARTNER CLOSELY WITH OUR CUSTOMERS ACROSS A WIDE RANGE OF INDUSTRIES TO MAXIMIZE THEIR R&D CAPABILITY AND PRODUCTIVITY, POWERING INNOVATION TODAY THAT IGNITES THE INGENUITY OF TOMORROW. You have spent the better part of your career translating product ambition into silicon reality. You know that the hardest part of any SoC is not the individual IP blocks, it is making them work together as a coherent system that actually ships. You think in subsystems, not just components. You have sat in enough bring-up sessions to know that the decisions you make today about interconnect topology, power domains, or protocol alignment will either save or cost your team six months down the line. You are comfortable walking into a room with conflicting requirements from software, verification, and implementation teams and walking out with an architecture that makes sense for all of them. You do not need perfect specs to start. You ask the right questions, model the critical paths, and make the call. You have a point of view on what makes a subsystem robust, and you are not afraid to push back when a proposal does not hold up under real-world constraints. At Synopsys, you will work on IP subsystems that power everything from automotive AI to 5G infrastructure, and the architecture decisions you make will matter.

Requirements

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field with 15+ years of overall semiconductor experience
10+ years in semiconductor design, IP integration, or SoC/subsystem architecture roles with proven track record of delivering complex subsystems to production
Deep expertise in Verilog and SystemVerilog for RTL design and simulation, with hands-on experience using industry-standard simulation tools
Strong working knowledge of interface protocols such as AMBA APB, AXI, CHI, DDR, PCIe, Ethernet, USB, or UFS, including protocol-level debugging and performance analysis
Experience with synthesis, lint, CDC, low power design flows, and verification closure using SystemVerilog UVM, BFM development, or test environment creation
Demonstrated ability to coordinate cross-disciplinary teams including hardware, firmware, software, verification, and physical design groups to drive complex projects to completion
Excellent technical writing and communication skills with a track record of producing clear architecture documents and specifications that drive alignment across diverse engineering teams

Nice To Haves

You can take a vague product requirement and turn it into a subsystem architecture that actually works, not just on paper but through bring-up, without creating downstream chaos for implementation or verification teams
You know how to make the hard tradeoff calls between performance, power, and area when the math does not give you a clean answer, and you can explain your reasoning to a VP in two minutes without losing the technical nuance
You are the person teams come to when a subsystem integration is not behaving as expected, because you can move between protocol-level details, dataflow analysis, and system-level constraints without losing the thread
You do not wait for perfect information to move forward, you build models, run scenarios, and de-risk the architecture early so the team can execute with confidence
You mentor without micromanaging, you help engineers think through architectural problems rather than just handing them answers
You stay current on industry trends, new protocols, and emerging SoC architectures because you know that what worked five years ago will not cut it for the next generation of products

Responsibilities

Define subsystem architectures for memory controllers, interconnect clusters, compute blocks, power management units, or communication subsystems, translating product requirements into detailed specs that balance performance, power, area, security, and functionality
Integrate multiple IP blocks into cohesive subsystems, ensuring proper interoperability, dataflow alignment, and interface compatibility with SoC-level interconnects and firmware requirements
Lead architecture exploration activities including IP selection, subsystem modeling, and validation of candidate architectures using simulation and analysis tools
Coordinate with SoC architects, verification teams, software engineers, and physical design groups to ensure subsystem feasibility, correctness, and alignment with platform constraints
Define verification requirements for subsystem functionality, performance corner cases, power states, and protocol compatibility, working with DV teams to ensure comprehensive validation coverage
Produce architecture documents, subsystem specifications, engineering guidelines, and implementation requirements that clearly communicate architectural intent to technical and non-technical stakeholders
Participate in silicon bring-up, debug sessions, and subsystem-level performance characterization to validate architectural decisions in real hardware