SOC Engineering, Senior Engineer

Synopsys•Gilbert, AZ

10d•$98,000 - $147,000•Hybrid

About The Position

Synopsys is a leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity. This role involves deep engagement with RTL code, turning specifications into working digital logic that synthesizes and meets timing. The focus is on creating clean, robust RTL that enables efficient verification and predictable implementation. The engineer will work on real SoC designs for customers building a variety of products, and their designs will go to silicon. The position is a hybrid role based in Gilbert, Arizona.

Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering
3 to 4 years of hands-on experience in ASIC or FPGA RTL design, implementation, and debug
Strong proficiency in Verilog, SystemVerilog, or VHDL RTL coding for registers, pipelines, state machines, memories, and FIFOs
Working knowledge of the ASIC design flow from micro-architecture through RTL development, synthesis, and timing closure
Ability to read a micro-architecture document, identify gaps or ambiguities, and ask clarifying questions before coding
Ability to write RTL with the downstream flow in mind, ensuring clean synthesis and meeting timing
Clear communication across teams and time zones
Organization in managing multiple tasks, tracking work, and following up on issues
Discipline in running checks and closing loops, ensuring lint is clean and CDC issues are resolved before handoff
Comfort working with teams in different geographies and adapting communication style

Nice To Haves

Experience using industry-standard tools such as simulators, lint checkers, CDC/RDC analysis tools, synthesis tools, and static timing analysis
An understanding of standard interface protocols including AXI, APB, AHB, I2C, and SPI
Experience with more complex protocols like PCIe, DDR, or Ethernet
Familiarity with SystemVerilog assertions, C++, or Python for verification or scripting tasks
Familiarity with low-power design methodologies and UPF
Familiarity with DFT requirements
Familiarity with Git-based development flows
Familiarity with formal verification tools
Familiarity with AI-assisted engineering tools and code-generation assistants

Responsibilities

Write and review Verilog, SystemVerilog, or VHDL RTL for block-level designs including state machines, pipelines, FIFOs, and memory controllers based on micro-architecture specifications
Run RTL quality checks using tools like linting, CDC/RDC analysis, and synthesis to ensure your design is clean before handoff to physical design
Collaborate with verification engineers to debug testbench failures, refine corner cases, and close coverage gaps
Work with physical design teams to resolve timing issues, optimize logic for synthesis, and support timing closure from netlist through signoff
Implement standard interface protocols including AXI, APB, AHB, I2C, and SPI within SoC subsystems
Use scripting in Python, Tcl, or shell to automate repetitive tasks in the design flow and improve team productivity
Participate in design reviews with cross-functional teams across the globe, clearly communicating design decisions and tradeoffs