AI SOC Architect

Majestic Labs • Los Altos, CA

10h

About The Position

Majestic Labs is a fast-moving US-Israeli AI startup building full-stack custom AI servers for large-scale inference and training. The company is seeking an experienced SoC Architect - AI Acceleration (RISC-V and Compute Cluster Development) to lead the architecture and integration of its compute subsystem. The role defines and optimizes RISC-V-based compute clusters, vector engines, and shared memory structures for high-performance AI workloads.

The architect collaborates with design, verification, compiler, and ML software teams to maximize performance per watt and support scalability across silicon generations. This is a hands-on technical leadership role at the intersection of hardware design, parallel compute, and AI acceleration.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in SoC or compute architecture, focused on AI acceleration or high-performance computing.
• Deep understanding of RISC-V architecture, vector extensions, and parallel compute design.
• Experience with multi-core cluster integration, shared memory hierarchies, and cache coherency protocols.
• Familiarity with matrix multiplication engines, SIMD/vector processors, and AI kernel optimization.
• Strong background in embedded systems architecture, system-level performance modeling, and debug methodologies.
• Excellent analytical, problem-solving, and communication skills.

Nice To Haves

• Experience designing custom RISC-V ISA extensions or AI-specific compute units.
• Hands-on experience in neural network mapping, tiling, and kernel scheduling.
• Familiarity with AXI, UALINK, HBM, or chiplet-based architectures for scalable AI compute.
• Contributions to open-source RISC-V or AI compute frameworks.
• Proven success in first-silicon AI or HPC SoC programs.
• Understanding of compiler design and low-level ML operator optimization.

Responsibilities

• Architect and define RISC-V compute clusters, including multi-core integration, interconnects, and memory subsystems.
• Design matrix multiplication and vector processing engines optimized for neural network and ML kernels.
• Define ISA extensions, microarchitecture, and system-level interfaces for AI acceleration.
• Develop strategies for compute task mapping, thread scheduling, and shared cache (L3) utilization.
• Collaborate with compiler and ML runtime teams on software–hardware co-optimization.
• Evaluate workload performance and power trade-offs using simulation and modeling.
• Define compute-subsystem debug, trace, and performance-monitoring features.
• Work with SoC, memory, and I/O architects to support cohesive dataflow and system efficiency.
• Provide specifications and technical guidance to RTL, verification, and firmware implementation teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior