Principal Memory Subsystem Architect

Advanced Micro Devices, Inc•GEORGIA, GA

3d•Hybrid

About The Position

The Memory Standards Architecture team seeks an LPDDR and DRAM Buffer Standards Architect to own AMD’s architecture strategy for low-power DRAM and advanced memory-buffer technologies. This architect will define AMD’s multi-generation LPDDR and DRAM-buffer roadmap; lead technical positions for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, and future buffer architectures; and represent AMD in JEDEC and the broader memory ecosystem. Serving Client, Server, Embedded, S3, and other adopting businesses, the architect will consolidate product, platform, design, validation, firmware, package, and system needs into unified AMD positions, supplier requirements, implementation specifications, and platform guidance.

Requirements

Recognized memory-technology expert who can move effectively between detailed device and interface architecture, system-level tradeoffs, industry standards, and executive decision-making.
Deep LPDDR and DDR knowledge.
Sound architectural judgment.
Demonstrated ability to align internal teams and external partners around technically rigorous, implementable positions.
Ability to communicate complex decisions clearly.
Ability to resolve competing technical priorities.
Ability to build consensus while considering performance, power, reliability, cost, interoperability, qualification, and schedule constraints.
Comfortable leading through influence across organizational and company boundaries.
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field required.
Master’s degree or PhD preferred.

Responsibilities

Define AMD’s multi-generation LPDDR and DRAM-buffer strategy, adoption plans, priorities, ownership, risks, and business-unit decisions across Client, Server, Embedded, S3, and other adopting organizations.
Represent AMD in JEDEC and related forums through technical proposals, ballots, negotiations, partnerships, and consensus building; maintain approved AMD positions and drive closure of standards dependencies.
Define requirements for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, future buffer architectures, and supporting components, including partitioning, topology, interfaces, protocols, clocking, performance, power, training, telemetry, reliability, security, test, error handling, recovery, and interoperability.
Coordinate DRAM and buffer behavior with controller, PHY, SoC, package, module, board, firmware, validation, and platform requirements; guide tradeoffs among discrete, module-level, in-package, die-integrated, DRAM-integrated, and host-side implementations.
Deliver architecture, SPD, configuration, authentication, attestation, firmware, power, thermal, packaging, platform, compliance, margining, characterization, robustness, and fault-handling requirements and guidance.
Align DRAM vendors and suppliers of buffers, PMICs, regulators, hubs, connectors, and related technologies on roadmaps, qualification plans, interoperability, readiness milestones, and adoption risks.
Serve as the company-wide architecture authority, lead internal workgroups, resolve technical tradeoffs, document decisions and ownership, and provide business-unit teams with specifications, reusable solutions, implementation guidance, issue resolution, and launch-readiness support.
Own AMD’s multi-generation LPDDR and DRAM-buffer architecture strategy, including adoption plans, priorities, risks, ownership, and business-unit decisions, and serve as the company-wide technical authority for LPDDR devices, registered clock drivers, and advanced DRAM-buffer technologies.
Develop and maintain AMD technical positions for JEDEC and related standards organizations, advancing standards work through proposals, ballots, technical negotiations, objection resolution, partnerships, and consensus building.
Define architectural requirements for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, future buffer architectures, and supporting components.
Establish requirements covering partitioning, topology, interfaces, protocols, command and data behavior, clocking, training, performance, power, telemetry, reliability, security, test, error handling, recovery, and interoperability.
Coordinate DRAM and buffer architectures with controller, PHY, SoC, package, module, board, firmware, validation, and platform requirements, evaluating tradeoffs among discrete, module-level, in-package, die-integrated, DRAM-integrated, and host-side implementations.
Deliver implementation requirements and guidance for architecture, SPD, configuration, firmware, authentication, attestation, power, thermal design, packaging, compliance, margining, characterization, robustness, and fault handling.
Align DRAM vendors and suppliers of buffers, PMICs, regulators, hubs, connectors, and related technologies on roadmaps, qualification plans, interoperability, readiness milestones, and adoption risks.
Lead cross-functional architecture workgroups, document decisions and ownership, resolve technical tradeoffs, drive closure of standards and implementation dependencies, and provide adopting teams with reusable solutions, specifications, implementation guidance, issue resolution, and launch-readiness support.